[STM32 Motor Vector Control] Record 11——DMA Transfer

DMA transfer:

Principle: DMA transfer copies data from one address space to another.

DMA transfers data, but does not need to occupy the MCU, that is, when transferring data, the MCU can do other things, such as multithreading. Data is transferred from peripherals to memory or from memory to memory. The DMA controller includes DMA1 and DMA2, of which DMA1 has 7 channels and DMA2 has 5 channels, which can be understood as a pipeline for transferring data. It should be noted that DMA2 only exists in large-capacity microcontrollers. 

work process:

1. DMA request 
If the peripheral wants to transfer data through DMA, it must first send a DMA request to the DMA controller. After the DMA receives the request signal, the controller will give the peripheral a response signal. When the peripheral responds and the DMA controller receives the response signal, it will start the DMA transfer until the transfer is completed. 
DMA has two controllers, DMA1 and DMA2. DMA1 has two controllers. DMA1 has 7 channels and DMA2 has 5 channels. The channels of different DMA controllers have different peripheral requests. 
2. Channel 
DMA has 12 independently programmable channels. DMA1 has 7 channels and DMA2 has 5 channels. Each channel corresponds to the DMA request of different peripherals. Although each channel can receive multiple peripheral requests, it can only receive one at the same time, not multiple at the same time. 
3. Arbiter 
When there are multiple DMA requests at the same time, it means that there is a problem of responding in order, which is managed by the arbitrator. The arbitrator manages DMA requests in two stages: the first stage belongs to the software stage, which can be set in the MDA_CCRx register. There are 4 levels: very high, high, medium and low priority. The second stage belongs to the hardware stage. If two or more DMA channel requests are set with the same priority, their priority depends on the channel number. The lower the number, the higher the priority. For example, channel 0 is higher than channel 1. In large-capacity products and interconnected products, the DMA1 controller has a higher priority than the DMA2 controller.

Configuration:

DMA_ InitTypeDef initialization structure 

typedef struct

{ 

uint32_t DMA_PeripheralBaseAddr; // peripheral address uint32_t

DMA_MemoryBaseAddr; // memory address uint32_t

DMA_DIR; //Transmission direction uint32_t

DMA_BufferSize; //Transfer number uint32_t

DMA_PeripheralInc; // Peripheral address increment mode uint32_t

DMA_MemoryInc; // Memory address increment mode uint32_t

DMA_PeripheralDataSize; // Peripheral data width uint32_t

DMA_MemoryDataSize; // Memory data width uint32_t

DMA_Mode; //Mode selection uint32_t

DMA_Priority; // Channel priority uint32_t

DMA_M2M; // memory to memory mode;

}DMA_Init TypeDef;

DMA data configuration:

void DMA_Config(void)

 {

 DMA_InitTypeDef DMA_InitStructure;

 RCC_AHBPeriphClockCmd(DMA_CLOCK, ENABLE); // Enable DMA clock

 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)aSRC_Const_Buffer; // Source data address

 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)aDST_Buffer; // target address

 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; // Direction: peripheral to memory (internal FLASH here)

 DMA_InitStructure.DMA_BufferSize = BUFFER_SIZE; // Transfer size

 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable; // Peripheral (internal FLASH) address increment

 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; // Memory address increment

 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; // Peripheral data unit

 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; // Memory data unit

 DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; // DMA mode, one-shot or loop mode

 //DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;

 DMA_InitStructure.DMA_Priority = DMA_Priority_High; // Priority: High

 DMA_InitStructure.DMA_M2M = DMA_M2M_Enable; // Enable memory to memory transfer

 DMA_Init(DMA_CHANNEL, &DMA_InitStructure); // Configure DMA channel

 DMA_Cmd(DMA_CHANNEL,ENABLE); // Enable DMA

 }

Call the RCC_AHBPeriphClockCmd function to start the DMA clock. The corresponding clock must be started before using the DMA controller. The source address and the destination address use the array first address defined previously. The amount of data to be transferred is determined by the macro BUFFER_SIZE. The source and destination address pointer addresses are incremented. The one-time transfer mode cannot be used for cyclic transfer because there is only one DMA channel. The priority can be set arbitrarily. Finally, call the DMA_Init function to complete the initialization configuration of the DMA. 

The DMA_ClearFlag function is used to clear the DMA flag. The code uses the transfer completion flag. Clear the transfer completion flag before use to avoid unnecessary interference. The DMA_ClearFlag function requires 1 parameter, namely the event flag. The optional options include the transfer completion flag, half transfer flag, FIFO error flag, transfer error flag, etc. There are many options. Here we choose the transfer completion flag, which is defined by the macro DMA_FLAG_TC. 

The DMA_Cmd function is used to start or stop DMA data transfer. It receives two parameters, the first one is the DMA channel, and the other one is ENABLE or DISABLE.

Main tasks completed:

1. Carefully comb through the FOC2.0 program;

2. A deeper understanding of the detailed process of startup detection and sampling;

3. Gain a deeper understanding of the sector judgment during ADC sampling and the programming of its injection method.

In general, the operation procedures of BLDC motors without Hall control in FOC2.0 have been roughly mastered, but there may still be some details that have not been discovered.

Next, we will use the motor running program with Hall control to further study FOC2.0