NVIC of stm32f407

5. NVIC

       The interrupt vector nesting controller is used to manage all interrupts and events, including interrupt enable and disable, and interrupt priority. This belongs to the kernel, so ST's reference manual has little description of it, but it is very important. To understand it, you need to read ARM's "Cortex™-M4 Devices Generic User Guide".

Related registers

Translated from "Cortex™-M4 Devices Generic UserGuide". If there are any errors, please refer to the original text.

Interrupt enable register NVIC_ISER[8]

There are 8 interrupt enable registers in total. ISER[0] sets the enable of interrupts 0 to 31, ISER[1] sets the enable of interrupts 32 to 63, and so on. The following takes ISER[0] as an example:

[31:0] SETENA Interrupt Set Enable Bit.
Write:
0 = No effect
1 = Enable interrupt.
Read:
0 = Interrupt is disabled
1 = Interrupt is enabled

To enable interrupt 0, write 1 to bit 0 of the register. To enable interrupt 38, write 1 to bit 6 of NVIC_ISER[1], and so on. For information on which interrupt corresponds to which interrupt number, refer to the Position column in Chapter 9, Table 30. Vector table in the reference manual "RM0090 Reference manual".

Interrupt disable register NVIC_ICER[8]

There are 8 interrupt disable registers in total. ICER[0] sets interrupts 0 to 31 to disable, ICER[1] sets interrupts 32 to 63 to enable, and so on. The following takes ICER[0] as an example:

[31:0] SETENA Interrupt Set Enable Bit.
Write:
0 = No effect
1 = Disable interrupt.
Read:
0 = Interrupt is disabled
1 = Interrupt is enabled

The following registers are all 8, only ***R[0] is used as an example

Interrupt pending setting register NVIC_ISPR[8]

[31:0] SETPEND interrupt pending set bit.
Write:
0 = No effect
1 = Change interrupt status to pending.
Read:
0 = Interrupt is not pending
1 = Interrupt is waiting to be processed.

Release interrupt pending register NVIC_ICPR[8]

[31:0] CLRPEND interrupt clear pending bit.
Write:
0 = No effect
1 = Remove pending state of interrupt.
Read:
0 = No interrupt is pending
1 = Interrupt is pending.

Interrupt activation bit register NVIC_IABR[8]

[31:0] Interrupt active flag:
0 = Interrupt inactive
1 = Interrupt active.

Reading this bit will read 1 if the corresponding interrupt status is as an active or active and pending.

Interrupt Priority Register NVIC_IPR[60]

       The interrupt priority registers are 60 32-bit registers, and the st structure uses 240 8-bit byte arrays NVIC->IP[240] to map them, each corresponding to an interrupt priority.

There are two types of ARM interrupt priorities: preemption priority and response priority.

        An interrupt with a high preemptive priority can be responded to during the interrupt processing with a low preemptive priority, that is, interrupt nesting, or an interrupt with a high preemptive priority can nest an interrupt with a low preemptive priority.

         When the preemptive priority of two interrupt sources is the same, there will be no nesting relationship between the two interrupts. When one interrupt arrives, if another interrupt is being processed, the later interrupt will have to wait until the previous interrupt is processed. If the two interrupts arrive at the same time, the interrupt controller decides which one to process first based on their response priority; if their preemptive priority and response priority are equal, the order of their ranking in the interrupt table determines which one to process first.

        Interrupt priority grouping is to divide the priority register, separating which bits are response priority and which bits are preemption priority. As for how to set the grouping, it depends on a register that does not belong to NVIC.

Application interrupt and reset control register SCB_AIRCR

What we need to look at here are bits [31:16] and [10:8]. Bits [31:16] are identification codes used to protect this register from accidental modification, and bits [10:8] are the setting bits for the interrupt priority grouping.

[31:16]

Write: VECTKEYSTAT
Read: VECTKEY
RW Registration key:
Read as 0xFA05
When writing, write 0x05FA to VECTKEY, otherwise the write will be ignored.

[10:8] Interrupt priority

Each ARM M4 interrupt priority is designed to be 8-bit programmable. Specifically, stm32f4 only leaves 4 bits of 16 levels of programmable priority for the user, of which the lower 4 bits are occupied. That is to say, the priority grouping of stm32f4 is shown in the following table:

The last NVIC register

Software trigger interrupt register NVIC_STIR

When the USERSETMPEND bit of SCB_CCR is 1, unprivileged user programs can write to this register.

[31:9] Reserved.
[8:0] INTID ID number interrupt trigger,
range 0-239. For example, 0x03 specifies interrupt IRQ3 trigger.