STC89C52MCU--Serial Communication Interface SPI

SPI is a full-duplex, high-speed, synchronous communication bus. It has two working modes: master mode and slave mode. In master mode, the transmission rate can reach 3mbps. When the system clock is 12Mhz, if the CPU uses a higher frequency, the rate can be higher. In slave mode, the speed cannot be too fast, usually within fsoc/8.

Data registers related to STC12 series microcontroller and SPI interface

SPCTL register function

SPSTAT register function

SPDAT.7 - SPDAT.0 -- Transmission data bits Bit7~Bit0

Looking at the SPI frame diagram, SPI has four pins: SPICLK/P1.7, MOSI/P1.5, MISO/P1.6, and SS/P1.4

The SPI clock divider selection is implemented through the SPR1 and SPR0 bits in SPCTL.

SPI write conflict: SPI is single buffered when transmitting and double buffered when receiving. If new data is written to the shift register when transmitting, WCOL will be set to indicate a data conflict; the written data will be lost and the data will continue to be sent. When the host or slave performs write conflict detection, the probability of a write conflict in the host is very low because the host has full control over the data transmission, but a write conflict may occur in the slave because the slave cannot control the transmission. When receiving data, the received data is transferred to a parallel read data buffer, which will release the shift register for the next data reception; but the received data must be read out before the next character is completely shifted in, otherwise the previous data will be lost.

For specific host connection configuration mode diagram, please refer to P299