LPC1768 Clock and Timer

The clock consists of 4 parts

1: CLKSRC: 01 in the example
   Select the clock source of PLL0 as follows:
  00 Select the internal RC oscillator as the clock source of PLL0 (default)
  01 Select the main oscillator as the clock source of PLL0
  10 Select the RTC oscillator as the clock source of PLL0
  11 Reserved, do not use this value

2: PLL0 configuration register (PLL0CFG – 0x400F C084)
FCCO = (2×M×FIN) / N // In the example, FCCO = 2×100×12Mhz / 6 = 100MHz

FIN The frequency of the PLL input clock in the clock source selection multiplexer
FCCO The system clock frequency (the output of the PLL current controlled oscillator)
N: The PLL0 prescaler value of the NSEL0 bit in the PLL0CFG register (PLL0CFG NSEL0 field + 1). N is an integer between 1 and 32
M: The PLL0 multiplier value of the MSEL0 bit in the PLL0CFG register (PLL0CFG MSEL0 field + 1).
Not all possible M values ​​are supported.

3: Re-division: CPU clock configuration register (CCLKCFG – 0x400F C104), the example here is 5 or 6 division. The division
value CCLKSEL can only be 0 and odd values ​​(1, 3, 5…, 255). CCLK is obtained from the output signal of PLL0 and divided by CCLKSEL+1

4: The clock input to the timer is divided again, in this case it is divided by 4

// Peripheral Clock Selection Register 0 (PCLKSEL0)
// PCLK_WDT: Peripheral Clock Selection for WDT
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// PCLK_TIMER0: Peripheral Clock Selection for TIMER0
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8

5: The clock obtained by the timer is 25mhz,

The timer can use PC and PR for re-division. In the example, here is 0, which means no more frequency division.

MR0 is the preset value. When a pulse comes, TC will increase by 1. When TC and MR0 are equal, the timer is triggered.

————》PR and PC ————> TC and MR0 --> Trigger