STM32 interrupt priority concept

I. Overview

STM32 currently supports a total of 84 interrupts (16 cores + 68 external), which can provide 16 levels of programmable interrupt priority settings (only using the upper 4 bits of the interrupt priority setting 8 bits) and 16 preemption priorities (because the preemption priority can be up to 4 bits).

2. Priority Judgment

There are two concepts of priority in STM32 (Cortex-M3) - preemption priority and response priority. The smaller the attribute number, the higher the priority. Some people call the response priority "sub-priority" or "sub-priority". Each interrupt source needs to be assigned these two priorities.
An interrupt with a high preemptive priority can be responded to during the processing of an interrupt with a low preemptive priority, that is, interrupt nesting, or an interrupt with a high preemptive priority can nest an interrupt with a low preemptive priority.
When the preemptive priorities of two interrupt sources are the same, there will be no nesting relationship between the two interrupts. When an interrupt arrives, if another interrupt is being processed, the later interrupt will have to wait until the previous interrupt is processed before it can be processed. If the two interrupts arrive at the same time, the interrupt controller decides which one to process first based on their response priority; if their preemptive priority and response priority are equal, it decides which one to process first based on their ranking order in the interrupt table.
3: Priority grouping
Since each interrupt source needs to be assigned these two priorities, there needs to be a corresponding register bit to record the priority of each interrupt; 8 bits are defined in Cortex-M3 to set the priority of the interrupt source. These 8 bits can be allocated in 8 ways in the interrupt priority grouping field of the NVIC Application Interrupt and Reset Control Register (AIRCR):
All 8 bits are used to specify the response priority.
The highest 1 bit is used to specify the preemptive priority, and the lowest 7 bits are used to specify the response priority.
The highest 2 bits are used to specify the preemptive priority, and the lowest 6 bits are used to specify the response priority. The
highest 3 bits are used to specify the preemptive priority, and the lowest 5 bits are used to specify the response priority. The
highest 4 bits are used to specify the preemptive priority, and the lowest 4 bits are used to specify the response priority. The
highest 5 bits are used to specify the preemptive priority, and the lowest 3 bits are used to specify the response priority. The
highest 6 bits are used to specify the preemptive priority, and the lowest 2 bits are used to specify the response priority.
The highest 7 bits are used to specify the preemptive priority, and the lowest 1 bit is used to specify the response priority.
This is the concept of priority grouping.

Cortex-M3 allows fewer interrupt sources to use fewer register bits to specify the priority of the interrupt source, so the STM32 reduces the register bits for specifying interrupt priority to 4 bits (the upper four bits of AIRCR). The grouping of these 4 register bits is as follows:
Group 0: All 4 bits are used to specify the response priority
Group 1: The highest 1 bit is used to specify the preemptive priority, and the lowest 3 bits are used to specify the response priority
Group 2: The highest 2 bits are used to specify the preemptive priority, and the lowest 2 bits are used to specify the response priority
Group 3: The highest 3 bits are used to specify the preemptive priority, and the lowest 1 bit is used to specify the response priority
Group 4: All 4 bits are used to specify the preemptive priority
You can select which priority grouping method to use by calling the function NVIC_PriorityGroupConfig() in the STM32 firmware library. This function has the following 5 parameters:
NVIC_PriorityGroup_0 => Select Group 0
NVIC_PriorityGroup_1 => Select Group 1
NVIC_PriorityGroup_2 => Select Group 2
NVIC_PriorityGroup_3 => Select Group 3
NVIC_PriorityGroup_4 => Select Group 4

The interrupt priority grouping is to allocate the number of bits occupied by each priority number in the upper four bits of the interrupt priority register to the preemptive priority and response priority. It can only be set once in a program.

4: Interrupt source priority

The next step is to specify the priority of the interrupt source. The interrupt source priority is set in the interrupt priority register. Only the upper four bits can be set. The corresponding value must be set in the register according to the number of bits set in the interrupt priority group. If you choose the third group of the interrupt priority group: the highest 3 bits are used to specify the preemptive priority, and the lowest 1 bit is used to specify the response priority, then the preemptive priority has eight data options from 000-111, that is, there are eight interrupt nests, and the response priority has two types of 0 and 1, a total of 8*2=16 priorities.

The interrupt source priority specifically sets the priority level of the interrupt source.

Multiple (up to 16) priorities can be set in one program, but only one can be set for each interrupt source.

Every interrupt priority program must include the following two functions:

1) void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup) interrupt group setting

2) void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) interrupt priority setting

Note: NVIC can configure 16 types of interrupt vectors, not 16. When there are more than 16 interrupt vectors in the project, there must be more than two interrupt vectors using the same interrupt type, and interrupt vectors with the same interrupt type cannot be nested.

5. Start the required GPIOn_Pin and AFIO RCC clock

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,RCC_APB2Periph_AFIO,ENABLE);

Note: Don't forget to enable RCC_APB2Periph_AFIO! Otherwise the pin can only be used as a normal high or low level. When using GPIO as EXTI external interrupt or using the remapping function, the AFIO clock must be enabled, but when using the default multiplexing function, the AFIO clock does not need to be enabled.

6. Examples

1. NVIC_InitTypeDef NVIC_InitStructure; //Define interrupt initialization type structure variable  

2.     

3.   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); //Configure priority group 1 2 preemptive priorities 8 sub-priorities  

4.   NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; //Open external interrupt 0  

5.   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; //Configure preemptive priority 0    

6.   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; //Sub-priority is configured as 0  

7.   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //Enable channel  

8.   NVIC_Init(&NVIC_InitStructure); //Initialize the configuration of external interrupt 0  

9.   

10.   

11.   NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn; //Open external interrupts 5 to 9  

12.   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; //Configure preemptive priority 1    

13.   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; //Sub-priority is configured as 1  

14.   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //Enable channel  

15.   NVIC_Init(&NVIC_InitStructure); //Initialize the configuration of external interrupt 0  

16.   

17.   

18.   NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;     //ADC1中断  

19.   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; //Configure preemptive priority 1    

20.   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; //Sub-priority is configured as 1  

21.   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //Enable channel  

22.   NVIC_Init(&NVIC_InitStructure); //Initialize the configuration of external interrupt 0  

23.   

From the above configuration, external interrupt 0 has the highest priority, which can interrupt ADC and external interrupts 5 to 9, that is, they can be nested. When the ADC interrupt and external interrupts 5 to 9 occur at the same time, their preemption priority levels are the same, and their sub-priority levels are also the same. Because the ADC1 hardware is ranked higher, the ADC interrupt occurs first. If any of the two interrupts is being executed, wait until the interrupt is executed before executing the other interrupt.

NVIC_InitStructure.NVIC_IRQChannel=EXTI9_5_IRQn indicates that the interrupt vectors of lines 5 to 9 of EXTI are to be configured, that is, lines EXTI5 to EXTI9 use the same interrupt vector. These writable parameters can be found in the stm32f10x.h file.