Design of MPEG-2 Coding System Based on SAA6752

    Digital television has developed very rapidly around the world. The entire process of television broadcasting, from shooting, production, transmission to broadcasting, is gradually being digitized. The emergence of the MPEG video/audio compression standard solves the problem of excessive information volume and limited channel bandwidth after digitization of television signals; the continuous advancement of digital video hardware products has promoted the launch of various digital video products, bringing high-quality picture and sound effects to the audience. All of this indicates that television broadcasting has fully entered the digital era.

    At present, the world's digital television system standards include the European DVB system, the American ATSC system and the Japanese ISDB system. These systems all use the MPEG-2 standard for video compression[2]. my country is also actively developing its own digital television standards. This article will introduce the SAA6752 chip produced by PHILIPS, which can implement MPEG-2 encoding in the development of European DVB standard conventional digital television and DVD front-end system products.

    1 Main features of SAA6752

    SAA6752, also known as EMPRESS, is the second generation of real-time MPEG-2 encoding chip from PHILIPS. It integrates audio, video encoding and multiplexing into one chip, and has powerful functions. The entire encoding system can be realized by adding simple related chips externally, thereby reducing system costs. At the same time, all video and audio compression algorithms run on the internal MIPS processor of EMPRESS, and the encoding software has been solidified in the chip. No additional software development is required, and the system main control chip can set the necessary encoding parameters through the I2C bus. In addition, since it solves the main problems in video encoding - noise filtering and motion prediction, it can achieve high-quality video encoding at low bit rates, thereby achieving the purpose of storing more video and audio information on the storage medium.

    The chip mainly provides the following functions[1]:

    (1) Video Compression

    • Real-time MPEG-2 encoding (MP@ML compliant)

    •Supported resolutions: D1, 2/3D1, 1/2D1 and SIF

    •Supports IPB, IP and I-frame encoding in all modes

    •Supported bitrate: 1.5～25Mbps (for I-frame encoding only)

    1.5～15Mbps (for IP frame encoding only)

    1.5～15Mbps(for IPB frame encoding only)

    •Supports CBR (Constant Bit Rate) and VBR (Variable Bit Rate)

    •With programmable GOP (Group of PICture ) structure

    (2) Audio Compression

    •AC-3 audio encoding: bit rate 256kbps or 384kbps

    •MPEG-1 Layer 2 audio encoding (16 or 20 bit): bit rate 256kbps or 384kbps

    (3) System reuse

    • Multiplexing of video and audio streams compliant with the MPEG Systems standard (ISO 13818-1)

    • Generate and output MPEG-2 Transport Stream (TS), MPEG-2 Program Stream (PS), Packetized Elementary Stream (PES) and Elementary Stream (ES) compliant with DVD, D-VHS and DVB standards

    •Generate and insert MPEG time stamps (PTS/ DTS /SCR/PCR)

    2 MPEG-2 Coding System Based on SAA6752

    2.1 System Block Diagram

    Because SAA6752 does not have an on-chip CPU, in order to implement the encoding function, it must be controlled by an off-chip CPU. All control of SAA6752 (such as bit rate control, PS stream and TS stream output, etc.) is completed through the I2C bus [3], which is very simple. Figure 1 shows the block diagram of the MPEG-2 encoding system based on SAA6752.

    The encoding system is mainly divided into video input part, audio input/output part, EMPRESS part, reset part, output interface, power supply part, and I2C and UART interfaces.

    2.1.1 Video input part

    The video input part provides two analog input interfaces, one for CVBS signal and the other for YC signal. This part can be completed by PHILIPS SAA7114, and all its controls are completed through the I2C bus.

    2.1.2 Audio Input/Output Section

    Since EMPRESS provides an audio I2S interface, this part mainly completes the function of converting analog audio into digital audio I2S signal.

    2.1.3 EMPRESS

    Since SAA6752 uses multiple processor modules, each processor and control module is independent of each other, so the data transmission between modules is mainly realized through FIFO memory or external SDRAM. The system uses 16Mbit or 64Mbit SDRAM. EMPRESS SAA6752 can generate packetized elementary streams, and its bit stream can be set according to different applications. One is the PES stream corresponding to the DVD format, and its bit rate is variable; the other is the PES stream corresponding to the TS, and its bit rate is constant.

    2.1.4 Reset section

    The system provides two reset modes: one is hard reset; the other is soft reset using I2C control software.

    2.1.5 Output interface

    The system provides two TS parallel output interfaces: one is TTL interface; the other is standard LVDS interface.

    2.2 Software Programming

    In order to control the encoding of EMPRESS, the I2C interface line is used to connect the system to the computer to achieve the purpose of computer control of EMPRESS chip and initialize SAA7114. All related operations are achieved by accessing registers through the I2C bus. In the I2C control software, the I2C read and write addresses of EMPRESS and SAA7114 need to be determined.

    EMPRESS I2C read and write address:

    (1) When the I2C select signal of EMPRESS is low, its I2C write address is 40H and its read address is 41H.

    (2) When the I2C select signal of EMPRESS is high, its I2C write address is 42H and its read address is 43H.

    SAA7114 I2C read and write address:

    (1) When the I2C select signal of SAA7114 is low, its I2C write address is 40H and its read address is 41H.

    (2) When the I2C select signal of SAA7114 is high, its I2C write address is 42H and its read address is 43H.

    In order to prevent the I2C address conflict between EMPRESS and SAA7114, set the I2C select signal of EMPRESS to low level , then the I2C write address of EMPRESS is defined as 40H; set the I2C select signal of SAA7114 to high level, then the I2C write address of SAA7114 is defined as 42H.

    The control software should implement the following I2C interface functions:

    (1)Void I2C_Read_One_Byte(int address, int subaddress, int value)

    This function mainly implements the reading of a byte of a given register. address determines the chip to be accessed, subaddress determines the register to be accessed, and value is the returned register value.

    (2)I2C_Write_One_Byte(int address, int subaddress, int value)

    This function mainly implements writing a byte to a given register. Address determines the chip to be accessed, subaddress determines the register to be accessed, and value is the value to be written to the register.

    (3)I2C_Read_Muiti_Bytes(int address, int subaddress, int count, int *buffer)

    This function mainly implements the reading of multiple bytes of a given register. address determines the chip to be accessed, subaddress determines the register to be accessed, and buffer returns multiple register values.

    (4)I2C_Write_Multi_Bytes(int address, int subaddress, int count, int *buffer)

    This function mainly implements writing multiple bytes to a given register. address determines the chip to be accessed, subaddress determines the register to be accessed, and buffer is the multiple register values ​​to be written.

    By calling these functions, the on-chip registers of EMPRESS and SAA7114 can be set via the I2C interface.

    Using I2C control software, you can modify parameters (PID, bit rate, etc.) to generate and output the required TS, PS, PES, ES streams. When the output bit rate is set to 5-9Mbit/s, you can get a higher quality video image.

    SAA6752 adopts noise filtering and motion estimation technology, so that the MPEG-2 encoding system based on SAA6752 can still provide high-quality encoding effect for the input signal with interference under low bit rate compression. This is particularly suitable for applications with low bit rate compression, such as DVD video burning and personal video recording.

    While ensuring high encoding quality, the design of the MPEG-2 encoding system based on SAA6752 is very simple and easy to implement. When using this chip to design an MPEG-2 encoding system, you only need to add a video A/D conversion chip, an audio A/D conversion chip and an external SDRAM to the periphery, and ordinary analog video and audio signals can be compressed into high-quality MPEG-2 video streams and MPEG-1 layer2 or AC-3 audio streams, multiplexed into PS or TS, and provided to storage or broadcast media. Since all video and audio encoding algorithms and software are running in the on-chip processor, fewer system control resources are required. The main control chip only needs to set the encoding parameters through the I2C bus, which does not require users to have more MPEG encoding experience or invest too much design cost, shortening the design cycle.

    Therefore, the low-cost and high-quality encoding system designed with SAA6752 can be widely used in new consumer digital video products.