Design of Embedded Video Processing System Based on MPC5200B

    With the development of science and technology, embedded processors have been widely used in communication equipment, consumer electronics, military electronics and other fields, and there are more stringent requirements on the processing speed, power consumption and operating temperature of the processor, especially in the application of automotive electronics, military electronics and so on.

    Freescale's MlPC5200B is a compact, low-power embedded processor that is unique compared to other embedded processors and can meet the above performance requirements. The MPC5200B integrates a high-performance MPC603e core that uses a superscalar architecture and can process 760 MIPS at a frequency of 400 MHz and a temperature range of -40 to 85°C. It can run at 264 MHz (500 MIPS) at 105°C, making it suitable for environments with higher temperature levels. In addition, the MPC603e core integrates a high-performance, double-precision floating-point unit (FPU) that can speed up complex mathematical operations in parallel with other key tasks. It can provide sufficient support for most video algorithms. In addition, the MPC5200B integrates a rich set of peripheral interfaces [1]. Its powerful functions meet the needs of automotive electronic system development and provide guarantees for system development.

    2 System Hardware Design

    The design of an embedded video processing system based on MPC5200B requires comprehensive communication, sufficient memory, debugging functions, and test display functions in terms of hardware. According to the design, this system is mainly composed of the main processor part, video signal input part, data storage part, display part, communication part, etc., as shown in Figure 1.

    The design of the main processor part mainly includes system power supply, PLL power supply circuit, clock circuit, software and hardware reset circuit, power-on reset circuit and download debugging circuit.

    The memory of the storage unit part mainly depends on the support of the microprocessor. The memory supported by MPC5200B mainly includes SDRAM, ROM, FLASH, SRAM, etc. The size of the capacity depends on the size of the kernel mapping, operating system, file system, etc.

    In the video input part, the analog video signal is input by the differential circuit, converted into a digital signal by the AD converter AD9883A, and then sent to the MPC5200 for processing.

    The communication interface circuit includes: human-machine interface and machine-machine interface, providing 1 Ethernet interface, 1 RS232 interface, 1 PCI interface, 1 I2C interface, etc.

    2.1 Storage System Design

    MPC5200B has two sets of external buses: SDRAM bus and LOCalPlus bus. SDRAM bus supports synchronous single-rate DRAM and dual-rate DRAM, and adopts burst reading mode to improve the bandwidth of SDRAM bus. The clock frequency of SDRAM bus is equal to the clock frequency of internal bus XLBus. LocalPlus bus can generally be connected with ROM, FLASH, SRAM and other peripheral devices.

    2.1.1 Connection between MPC5200B and SDRAM

    MPC5200B has 16kB of SRAM inside, but needs to expand external memory, which is connected to external SDRAM through SDRAM controller. SDRAM is used to store data to be processed by the system. This system uses two MT48LCl6M16A2 SDRAM memories from MICRON. MT48LCl6M16A2 is powered by 3.3V and supports self-refresh mode. It refreshes once every 8192 SDRAM clock cycles (64ms). Its capacity is 256Mb and can be configured as 64M×4b, 32M×8b, and 16M×16b. Two SDRAMs can form an external SDRAM memory of 16M×32b. The connection schematic is shown in Figure 2.

    When the power is on and reset, the SDRAM bus is invalid, that is to say, the chip select signal of the SDRAM is invalid, so when powering on, the initialization register must be configured first to make the chip select signal of the SDRAM valid, and then data can be read from the SDRAM bus to make the system run normally.

    After SDRAM is powered on for 100 to 200 μs, an initialization process must be performed to configure the SDRAM mode register. The value of the mode register determines the working mode of SDRAM. The specific operation steps are as follows:

    (1) Determine the space of the SDRAM chip select signal CS#;

    (2) Calculate the values ​​of memory and controller registers based on SDRAM parameters and clock frequency;

    (3) Write the mode register and control register of SDRAM.

    2.1.2 Connection between MPC5200B and FLASH

    FLASH uses AMD's AM29LV065D, with a capacity of 8M×8B, supporting 3.0~3.6V read, erase and program operations, and is used to store the system's boot program. The connection schematic diagram with MPC5200B is shown in Figure 3. The chip AM29I.V065D has 23 address lines and 8 data lines, so the connection between MPC5200B and AM29LV065D can adopt nonMUXed mode. The high 8 bits AD[31:24] of the LocalPlus bus of MPC5200B are connected to the data line of FLASH as the data line, and the low 24 bits AD[23:0] of the bus are connected to the address line of FLASH as the address bus.

    Because after the system is powered on, the system starts from the storage device connected to LPCS0, so when FLASH is used as BootROM, the chip select signal CE# must be connected to the LPCS0 pin of MPC5200B.

    FLASH is a slow device and requires some wait states, so at each boot, the longest default time is required to start the MPC5200B. The longest wait state is 48 PCIClocks (i.e. 727ns, when the LocalPlus frequency is 66MHz).

    2.2 Design of communication interface

    The main function of the communication interface is to realize information interaction and data transmission between human and machine, machine and machine. The main design includes the following points:

    The Ethernet transceiver uses Intel's chip LXT972A, which is connected to the Ethernet port controller of MPC5200B. RXCLK and TXCLK: receive and transmit clock signals, provided by LXT972A, connected to the Ethernet controller port of MPC5200. RXD[3:O], TXD[3:O]: receive and transmit signals, provided by MPC5200, connected to RXD and TXD13 of LXT972A. TXEN: transmit enable signal. COL: conflict detection signal, driving the conflict detection input of the controller.

    The main function of the PCI interface controller is to realize data transmission between the main processor and the video input part. The data address bus of PCI is multiplexed, which is the data address bus of LocalPlus bus of MPC5200B, and the control signal line of PCI is provided by the PCI controller of MPC5200.

    The RS232 transceiver used is MAX3232 from MAXIM, which is connected to the UART port of MPC5200B.

    2.3 Interface design with LCD controller

    The LCD controller uses the liquid crystal control chip S1D13806 from Epson. The S1D13806 is a highly integrated color LCD/CRT/TV image controller with 1280kb of SDRAM integrated inside. It supports multiple CPU interfaces. The architecture of the S1D13806 meets the requirements of low voltage and low power consumption of embedded systems. The S1D13806 has 21 address lines and 16 independent data lines. The connection mode with the LocalPlus bus can be a mixed mode. Because the bus of the MPC5200B multiplexes the data and address lines, an address latch is required to latch the address. The connection diagram is shown in Figure 4.

    MPC5200B has three basic reset signals: power-on reset, internal/external hardware reset, and internal/external software reset.

    The system power-on reset time must be maintained for at least 35μs after power-on so that the system clock signal can tend to a stable state. The hardware and software reset signals must maintain a low level for 4095 clock cycles.

    When the external hardware reset signal HRESET# is valid, the internal reset logic captures the external reset signal as low level, and keeps the internal hardware reset and software reset signals at low level for 4095 clock cycles. Only when the external hardware reset signal maintains the valid level for at least 4 clock cycles can it be confirmed as a valid reset signal. The register in the clock distribution module (CDM) of MPC5200B has a software reset setting bit, which can be set by the microprocessor. When the software reset bit in this register is set to 0, it will cause external and internal software reset [1].

    3. System BSP Configuration

    After the hardware system design is completed, the embedded system design must be carried out. VxWorks is widely used in various embedded systems due to its superior performance.

    3.1 Overview of BSP

    3.1.1 Functions of BSP

    (1) Initialization

    CPU initialization initializes the CPU internal status registers, control registers, cache, etc.

    The target machine initializes the registers of the control chip (such as BUS, DMA , DRAM) and I/O registers to provide hardware environment support for the upper-level software system.

    System resource initialization initializes the operating system and performs resource initialization for the normal operation of the operating system.

    (2) Provide VxWorks with hardware driver programs and related device initialization operations.

    (3) Integrates hardware-related software and some hardware-independent software.

    3.1.2 Composition of BSP

    BSP consists of header files, source files, makefiles, and derived files.

    3.2 Debugging process

    The system is designed using the Bootrom plus VxWorks method, which has its unique advantages, such as adaptability to hardware and convenience for on-site debugging.

    The debugging tools used in this system are WindRiver's debugging software visionCL IC K and simulator WindRiverICE. The specific steps are as follows:

    (1) Connect the emulator and target board, mainly the power supply , serial port, and JTAG port.

    (2) After powering on, connect the serial port of the emulator to the RS232 serial port of the computer, open the HyperTerminal, and press the reset button of the emulator. You can see the relevant information of the emulator in the HyperTerminal. Mainly look at the IPAddress. The IP address of the host should be in the same IP segment as the IP address of the emulator. You can run the help command in the HyperTerminal and see various commands, all of which can be run. Run the "eth-setup" command to change the IP address of the emulator.

    (3) Open visionCLICK, create a new project, and follow the prompts to set the following: configurationfile, symbolfile, downloadfile, and sourcepath. Leave the other options as default. Generate bootromuncmp.ab and bootrom_unemp.bdx.

    (4) Connect the simulator, download, and run. After the prompt is correct, you can observe the values ​​of registers, memory, and other units in each window and debug. If there is an error, modify the source code, restart the compilation and download until it is completely correct.

    After debugging the BootROM, connect the Ethernet port of the target board to the network port of the host. The BootROM will automatically boot from the network port and load the compiled VxWorks to the target board for debugging. Finally, after everything is completed, both the BootROM and VxWorks are solidified to the target board for offline operation.

    4 Conclusion

    After the hardware design of the system is completed, the embedded operating system VxWorks is transplanted on the hardware basis of the embedded video processing system based on MPC5200B, and then the relevant drivers and applications are developed, and the corresponding video image processing algorithm is selected to realize a complete embedded video processing system. The experimental results show that the system meets the requirements of video signal processing. With the development of science and technology, embedded computers are widely used in consumer electronics, communication equipment, industrial control and military electronics, so the application prospects of this system are very broad.