Method of Expanding High-Speed ​​Serial Synchronous Shift Output Port of AT89C51 Single-Chip Microcomputer

The serial port of the AT89C51 (compatible with MCS-51) microcontroller can expand multiple 8-bit parallel I/O ports using a shift register chip in mode 0. In the LED dot matrix display application system, the data synchronous shift output method is generally adopted, and the shift register chip (such as 74LS595) is used to expand the parallel I/O port to drive the LED dot matrix display. The LED dot matrix display adopts a scanning method. In order to avoid flickering, 50 screens of dot matrix display data need to be transmitted per second. Therefore, a large amount of data needs to be sent to the display drive circuit part through synchronous shifting, which requires the microcontroller to output data quickly. The serial port of the AT89C51 microcontroller is in mode 0. The data is output at a baud rate of fosc/12. After 1 byte of data is written to SBUF, it is necessary to check whether the interrupt flag TI is "1" and clear "0" TI or delay several machine cycles before continuing to write a data. The output speed is slow. In the LED dot matrix display application system, the communication between the system and the PC needs to use the serial port of the microcontroller, and the synchronous shift output port of the display data can only be expanded separately. The high-speed serial synchronous shift output port (hereinafter referred to as the extended serial port) circuit introduced in this article adopts modular design and provides implementation solutions based on TTL and PLD circuits. The baud rate is increased to fosc, and data output does not require waiting or delay.

1. Extend the connection between the serial port and the microcontroller

The block diagram of the extended serial port circuit is shown in Figure 1. Similar to the parallel memory chip, the extended serial port is regarded as an external RAM address unit, directly connected to the external data bus of AT89C51, D0~D7 are data lines, CE is the chip select signal, WE is the write pulse signal, and also the output control signal of the extended serial port. The oscillation signal of the AT89C51 external crystal oscillator is shaped by two NAND gates to provide the clock pulse XTAL2 for the extended serial port. DAT and CLK are the data output terminal and synchronous shift pulse output terminal of the extended serial port respectively.

2. Operation Instructions

Assume that the address assigned to the extended serial port by AT89C51 is 0000H, use MOVX@DPTR, A or MOVX@R0, A instruction to write data into the extended serial port and shift the data. The following program segment sends 32 bytes of data with the first address of the internal RAM data area being 30H to the extended serial port for synchronous shift output:
MOV P2, #00H; Set the high 8 bits of the extended serial port address
MOV R1, #30H; Set the first address of the internal RAM data area
MOV R7, #32; Output the number of bytes
LOOP: MOV A, @R1; Read 1 byte from the internal RAM data area
INC R1; Point to the next address unit of the internal RAM data area
MOVX @R0, A; Send data to the extended serial port for output
DJNZ R7, LOOP; 32 bytes have not been sent and continue
RET

3. Design scheme and working principle based on TTL circuit

Figure 2 is an extended serial port circuit implemented with TTL circuit. 74LS74 is a dual rising edge D flip-flop with preset and clear functions. D1~D5 constitute an 8-pulse generator (counter principle). 74LS165 is an 8-bit parallel input serial output shift register. When the CPU executes the MOVX@R0, A (or MOVX @DPTR, A) instruction, the data is latched in the 74LS165. The timing of generating 8 pulse signals is shown in Figure 3. In Figure 3, Q0~Q5 are the output ends of 6 D flip-flops respectively. The extended serial port chip select is valid (CE=0). When the write pulse WE arrives, WR=0. At the rising edge of the clock pulse XTAL2, the output Q0 of the flip-flop D0 is 0, and Q0 resets Q5, making Q5=1; after the write pulse ends, WR=1, then WR·Q5=1, the reset end of the counter is invalid, the counter starts counting, and outputs a square wave pulse at the Q1 end; after the 8th pulse ends, Q5=1, then WR·Q5=0, the counter is reset, stops counting, and waits for the next write pulse. The 8 pulses output from the Q1 terminal are connected to the CLK2 (pin 15) of the 74LS165 as synchronous shift pulses, and are also the synchronous shift pulse output signals of the extended serial output port: the data latched in the 74LS165 by the MOVX instruction is output from the data terminal (DAT) of the extended serial output port under the action of the synchronous shift pulse (CLK).

4. Design scheme based on PLD circuit

Using programmable gate array devices to design circuits can simplify circuits and reduce the number of devices. The 8-pulse generator circuit in the dotted box in Figure 2 can be realized with one GAL16V8D, as shown in Figure 4. XTAL2 is the extended serial port clock pulse input signal, WR is the write pulse signal when the chip select is valid, and Q1 is the 8-pulse output terminal. Write the logical expression of Q1~Q5 according to the timing diagram shown in Figure 3. The following is an example of the logic design of the GAL16V8D chip.

AFT16V8D
NAME: ED13_U00
AUTHOR: FUHAO
DATE: 04.15.1999
; 1 2 3 4 5 6 7 8 9 10 (pin)
CLK WR NC NC NC NC NC NC NC GND
; 11 12 13 14 15 16 17 18 19 20 (pin)
OE Q1 Q2 Q3 Q4 Q5 NC NC NC VCC
Q1：=/Q1*WR*/Q5
Q2：=/Q2*Q1*WR*/Q5
+Q2*/Q1*WR*/Q5
Q3：=/Q3*Q2* Q1*WR*/Q5
+Q3*/Q2*WR*/Q5
+Q3*/Q2*WR*/Q5
Q4：=/Q4*Q3*Q2*Q1*WR*/Q5
+Q4*/Q3*WR*/Q5
+Q4*/Q2*WR*/Q5
+Q4*/Q1*WR*/Q5
Q5：=/ Q5*Q4*Q3*Q2*Q1*WR
+Q5*/Q4*WR + Q5
*/Q3*WR
+Q5*/Q2*WR
+Q5*/Q1*WR
DESCRIPTION
 

The method of expanding the high-speed serial synchronous shift output port of the microcontroller introduced in this article, as well as the implementation scheme based on TTL and PLD circuits, have been successfully applied in the LED dot matrix display system. The expansion serial port adopts modular design and is easy to transplant to other application systems.