1) Working power supply and ground
Vcc (40): power supply +5V±0.5V
Gnd (20): ground
2) Clock
XTAL1 (19): internal oscillator input
XTAL2 (18): internal oscillator output
Figure 2 Two clock circuits: (a) internal clock mode, (b) external clock mode.
1) Parallel I/O port
①P0.0 — P0.7 (39-32) General I/O port P0 / A0-A7 / D0-D7.
②P1.0 — P1.7 (1-8) General I/O port P1
③P2.0 — P2.7 (21-28) General I/O port P2 / A8-A15
④P3.0 — P3.7 (10-17) General I/O port P3 / Second function
P3.0 (10): RXD serial port data reception
P3.1 (11): TXD serial port data transmission
P3.2 (12): INT0 external interrupt 0
P3.3 (13): INT1 external interrupt
P3.4 (14): T0 counter/timer 0 external count pulse input
P3.5 (15): T1 counter/timer 1 external count pulse input
P3.6 (16): WR external data memory write control signal
P3.7 (17): RD external data memory read control signal
1) Control signal
① ALE (30): Output positive pulse, 1 is valid, external address latch signal.
How does port P0 serve as both address line and data line?
② EA (31): Input, 0 is valid, the first 4k selects the control signal of the external program memory.
How to select internal/external program memory for the first 4k?
③ PSEN (29): Output, 0 is valid, selection signal for accessing external program memory.
④ WR (16): External data memory write control signal
⑤ RD (17): External data memory read control signal
⑥ RST (9): Input, high level is valid for 24 clock cycles, generating a reset operation.
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Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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