ARM interrupt handling and interrupt controller

ARM has seven modes, and we will only discuss SVC, IRQ and FIQ modes here. We can assume that the ARM core has two interrupt pins (actually invisible), one is called irq pin, and the other is called fiq pin. In the ARM cpsr, there is an I bit and an F bit, which are used to disable IRQ and FIQ respectively. Let's not talk about the interrupt controller, just talk about the ARM core. Under normal circumstances, the ARM core just mechanically follows the instructions of the pc to do things. When the I and F bits in the CPSR are 1, IRQ and FIQ are all in a disabled state. No matter what kind of interrupt signal you send on the irq pin and fiq pin, ARM will not pay attention to you. You can't interrupt it at all, because it is deaf and blind. When the I bit and F bit are 0, when there is an interrupt signal on the irq pin, it will interrupt the current work of the arm, switch to IRQ mode, and jump to the corresponding exception vector table (vector) position to execute code. This process is automatic, but you have to do it yourself to return to the place where the interrupt was interrupted. When you jump to the exception vector table and are in IRQ mode, if an interrupt signal comes from the irq pin again, ARM will ignore you. The irq pin is like a secretary, and the ARM core is like a boss. The boss is working, but a customer comes. The secretary interrupts and lets the customer in. If another customer comes at this time, either the secretary keeps knocking on the door to ask, or the customer leaves. The boss will ignore you if he has not finished meeting with the first customer. But there is an exception. When ARM is in IRQ mode, an interrupt signal comes from the fiq pin. What is the fiq pin? It is a fast interrupt. For example, if the police come to investigate a criminal case, they don’t care whether your boss is meeting with a customer or not. They will interrupt directly, enter the fiq mode, and jump to the corresponding fiq exception vector table to execute the code. If the ARM is processing the FIQ mode, the fiq pin will interrupt again, which means another group of police are coming. There is no hope. They are all law enforcement officers. You can’t stop me. What if the irq pin comes at this time? I won’t pay attention to it. I am investigating a case, and I dare to interfere with public affairs. So we can draw a conclusion: IRQ mode can only be interrupted by FIQ mode, and no one can interrupt FIQ mode. If it cannot be interrupted, it is useless to send interrupt signals to irq pin or fiq pin. So except for fiq that can interrupt irq, there is no so-called interrupt nesting. But no matter how to say it, irq pin and fiq pin add up to only 2 pins, so what should we do with so many interrupt sources? It is impossible for everyone to knock on the door directly. So who should send signals to irq pin or fiq pin next? As can be seen in the above text, it is the boss's customer, or it may be the police. This matter is managed by the interrupt controller. Take the simplest 2410/2440 interrupt controller as an example. This interrupt controller plus a sub-interrupt controller and an external interrupt controller manage more than 50 interrupt resources, which means there are more than 50 pins. These pins have specified functions except for external interrupts, such as WDT, LCD, DMA, etc. This function cannot be changed because it is determined by the internal hardware connection of 2410/2440. When both WDT and DMA interrupts arrive, they will be sent to the SRCPND register. Both interrupts are in it, so which one should be sent to ARM? At this time, first look at INTMOD, that is, the mode. Which one is set as a fast interrupt, and which one will be sent up; what if both are set as fast interrupts? Impossible, because only one interrupt can be set as a fast interrupt at the same time. Therefore, if there is a fast interrupt, then the interrupt signal is directly sent to the fiq pin to interrupt ARM. If there is no fast interrupt, then look at INTMSK to see if WDT and DMA are masked. If DMA is masked in INTMSK, then only WDT continues to be sent up. If neither is masked, then they both go to the PRIORITY priority register. Here, according to the priority setting, one high and one low priority will be separated. The high one will be sent up and sent to the INTPND register, so INTTPND has only one interrupt in it at any time. As long as there is an interrupt in INTPNDD, the irq pin will not keep sending interrupt signals to the ARM. When the interrupt is sent for the first time, the ARM is interrupted. At this time, the ARM enters the corresponding exception vector and is in IRQ mode. At this time, INTPNDD is still sending interrupt signals to the ARM through the irq pin, but the ARM is already in IRQ mode and will not pay attention to you. When you have finished processing the interrupt and want to exit the IRQ mode, be careful at this time. If you do not clear the interrupt bit in INTPND before exiting the IRQ mode, you will be interrupted again when you just exit the IRQ mode, because INTPND is still sending interrupt signals. Therefore, you must clear the interrupt bit in INTPND before exiting the IRQ mode. However, clearing the bit in INTPND is not enough, because the WDT and DMA interrupts in SRCPND are still there. When you just clear INTPND, another one is selected from SRCPND and sent to INTPND. So the correct way to handle it is to clear the corresponding interrupt bit in SRCPND before exiting IRQ mode, and then clear the corresponding bit in INTPND. Please note that there may be multiple bits in SRCPND, so just clear the interrupt you have handled, while there may be only one bit in INTPND, so just clear it directly. Let's talk about the situation of Linux. Linux does not use FIQ, but only IRQ. But sometimes we need to handle an interrupt for a long time, so do we need to occupy IRQ mode for that long? No, Linux simply records what interrupt it is in IRQ mode and immediately switches back to SVC mode. In other words, Linux interrupt processing is all processed in SVC mode. So where does the interrupt number come from? It is fixed on ARM, and there is only one way to get the corresponding interrupt number: query irqs.h. Then I use an interrupt number to register an interrupt handler. When an interrupt occurs, how does Linux know that it is an interrupt with my interrupt number? When processing an interrupt, first read INTPND, then read EINTPEND or SUBSRCPND as needed to calculate an interrupt number. The corresponding processing algorithm is in the macro get_irq_nr_base. And the interrupt number in irqs.h is calculated according to this algorithm for each interrupt.