How to start

For S3C2440, there are two ways to boot, one is Nor Flash boot, the other is Nand Flash boot.

Boot using Nor Flash

The address range of Nor Flash is as follows

   0x0000.0000—0x0800.0000 (2M Nor Flash)

   The BootSRAM address on the chip is set to

   0x4000.0000—0x4000.DFFF (4K BootSRAM)

Since the code can be run directly in Nor Flash, BootSRAM is mapped to other addresses and can be used for other purposes.

The program image is directly stored in NOR FLASH, and the interrupt vector table is stored in the 8×4 space starting at 0x0000.0000.

When an interrupt occurs, the PC is set to the corresponding vector address. When the power is turned on or the reset key is pressed, the PC is directly set to 0x00 and execution starts from 0x00 of the NOR FLASH.

Booting using NAND Flash

At this time, the BootSRAM address in the chip is set to

   0x0000.0000—0x0800.0000 (4K BootSRAM)

   NAND Flash address connected to NFCE

Since the code cannot be run in NAND Flash, it must be copied to the memory and then run.

      The program image is stored in NAND FLASH, and the interrupt vector table is located at the front of the program image. Since NAND FLASH cannot run code, when the system is powered on or reset, the built-in NAND FLASH will access the control interface and automatically load the interrupt vector table and boot code into the internal SRAM (the SRAM is located at the starting address space 0x00000000, with a capacity of 4KB), and set the PC value to 0x00 to run the program (all this is done by the hardware logic inside the chip). After that, the boot program in SRAM loads the operating system image into SDRAM, and the operating system can run in SDRAM. After the startup is completed, the 4KB startup SRAM can be used for other purposes.

Interrupt vector table settings

There are 7 types of exceptions and interrupts in ARM

 

Response priority from high to low	According to the interrupt vector table order
Reset	Reset
Data abort	Undefined instruction interrupt
FIQ	SWI
IRQ	Prefetch instruction abort
Prefetch instruction abort	Data Abort Exception
Undefined instruction, SWI	IRQ
	FIQ

      ARM requires that the interrupt vector table must be placed in a continuous 8×4-byte space starting from address 0 (ARM720T, ARM9, and ARM10 also support high-address vector tables starting from 0xFFFF0000). The locations of each exception and interrupt vector in the vector table are as follows

 

address	Interrupt
0x00	Reset
0x04	Undef
0x08	SWI
0x0C	Prefetch Abort
0x10	Data Abort
0x14	(Reserved)
0x18	IRQ
0x2C	FIQ

      When an interrupt occurs, the ARM processor forces the PC pointer to be set to the corresponding vector address in the interrupt vector table. Because each interrupt vector has only one byte of storage space in the vector table and can only store one instruction, a jump instruction is usually stored to make the program jump to other places in the memory and then execute the interrupt processing.

 

The implementation procedure of the interrupt vector table is usually as follows AREA Boot, CODE, READONLY ENTRY B Reset_Handler; Reset_Handler is a label B Undef_Handler B SWI_Handler B PreAbort_Handler B DataAbort_Handler B ;for reserved interrupt, stop here B IRQ_Handler B FIQ_Handler

      The keyword ENTRY specifies that the compiler should keep this code, because the compiler may consider this code to be redundant and optimize it. When linking, make sure that this code is linked to address 0 and used as the entry point of the entire program (ENTRY is not always used to set the entry point of the program, so it is usually necessary to explicitly set the program entry point in the link options).