MSP430 Functional Module Detailed Explanation Series - ADC12

1. ADC12 conversion mode

ADC12 provides 4 conversion modes:

Single channel single conversion

To perform a single conversion on the selected channel, the following settings are required:
x = CSStartAdd, pointing to the conversion start address
ADC12MEMx stores the conversion result
ADC12IFG.x is the corresponding interrupt flag
ADC12MCTLx register defines the channel and reference voltage
When the conversion is completed, ENC must be reset and set again (rising edge) to prepare for the next conversion. The input signal before ENC is reset and set again will be ignored.

Sequential channel single conversion

To perform a single conversion on a sequence channel, the following settings are required:
x = CSStartAdd, indicating the conversion start address
EOS (ADC12MCTLx.7) = 1 marks the last channel y in the sequence, and the EOS bit of non-last channels is 0, indicating that the sequence has not ended.
ADC12MEMx, ... ADC12MEM.y store the conversion results
ADC12IFG.x, ... ADC12IFG.y are the corresponding interrupt flags .
The channel and reference voltage are defined in the ADC12MCTLx register.
When the conversion is completed, ENC must be reset and set again (rising edge) to prepare for the next conversion. The input signal before ENC is reset and set again will be ignored.

Single channel multiple conversions

Perform multiple conversions on the selected channel until the function is turned off or ENC=0. Set as follows:
x=CSStartAdd, pointing to the conversion start address
ADC12MEMx to store the conversion results. 
The channel and reference voltage are defined in the ADC12MCTLx register.
In this mode, you can change the conversion mode without stopping the conversion first. You can change the conversion mode after the current conversion is completed. There are several ways to stop this mode:
Use CONSEQ=0 to change to single-channel single-shot mode.
Use ENC=0 to stop the current conversion directly after completion.
Replace the current mode with single-channel single-shot mode and set ENC=0 at the same time

Multiple conversion of sequence channels

Convert the sequence channels multiple times until the function is turned off or ENC = 0. Set as follows:
x = CSStartAdd, indicating the conversion start address
EOS (ADC12MCTLx.7) = 1 marks the last channel y in the sequence. 
The ADC12MCTLx register defines the channel and reference voltage
change conversion mode, without having to stop the conversion first. Once the mode is changed (except single-channel single-shot mode), it will take effect immediately after the current sequence is completed.

Regardless of which conversion mode you use, you must deal with the following issues:

Set the specific mode
, input the analog signal,
pay attention to the conversion end signal,
store the conversion data, and read the data by query or interruption.

2. ADC12 Register Description

1. ADC12CTL0 control register 0, each bit definition:

ADC12SC - sampling/conversion control bit. Under different conditions, the meaning of ADC12SC is as follows:

ENC - conversion enable bit.

0: ADC12 is in the initial state and A/D conversion cannot be started;
1: The first conversion is started by the rising edge of SAMPCON

ADC12TVIE——Conversion time overflow interrupt enable bit (if another sampling request occurs before the current conversion is completed, a conversion time overflow will occur)

0: No conversion time overflow occurred
1: Conversion time overflow occurred

ADC12OVIE - Overflow interrupt enable bit (when the original data in ADC12MEMx has not been read out, and there is new conversion result data to be written, an overflow occurs)

0: No overflow occurred
1: Overflow occurred

ADC12ON——ADC12 core control bit

0: Disable ADC12 core
1: Enable ADC12 core

REFON——reference voltage control bit

0: Internal reference voltage generator is off
1: Internal reference voltage generator is on

2.5V - internal reference voltage voltage selection bit

0: Select 1.5V internal reference voltage
1: Select 2.5V internal reference voltage

MSC - Multiple sampling conversion bit (CONSEQ<>0 means the current conversion mode is not single channel single conversion)

SHT1, SHT0——Sample and hold timer 1, sample and hold timer 0

The relationship between the conversion sampling timing and the sampling clock ADC12CLK stored in the conversion result registers ADC12MEM8~ADC12MEM15 and ADC12MEM0~ADC12MEM7 is defined respectively. The sampling period is an integer multiple of the ADC12CLK period multiplied by 4, that is:

2. ADC12CTL1 conversion control register 1 (mostly 3 to 15 bits, can only be modified when ENC=0), each bit definition:

CSSTARTADD——Conversion memory address bit. The binary numbers 0 to 15 represented by these 4 bits correspond to ADC12MEM0 to 15 respectively. It can define a single conversion address or the first address of a sequence conversion.

SHS——Sampling trigger input source selection bit.

0: ADC12SC
1: Timer_A.OUT1
2: Timer_B.OUT0
3: Timer_B.OUT1

SHP - sampling signal (SAMPCON) selection control bit.

0: SAMPCON is derived from the sampling trigger input signal
1: SAMPCON is derived from the sampling timer, and the sampling timer is triggered by the rising edge of the sampling input signal

ISSH——Sampling input signal direction control bit

0: The sampling input signal is the same direction input
1: The sampling input signal is the reverse direction input

ADC12DIV——ADC12 clock source frequency division factor selection bit. The frequency division factor is the 3-bit binary number plus 1

ADC12SSEL——ADC12 core clock source selection

0: ADC12 internal clock source - ADC12OSC
1: ACLK
2: MCLK
3: SMCLK

CONSEQ - Conversion mode selection bits

0: Single channel single conversion mode
1: Sequential channel single conversion mode
2: Single channel multiple conversion mode
3: Sequential channel multiple conversion mode

ADC12BUSY——ADC12 busy flag (only used in single-channel single conversion mode, in other conversion modes, this bit is invalid)

0: Indicates no active operation
1: Indicates that ADC12 is in the sampling period, conversion period or sequence conversion period

3. ADC12MEM0~ADC12MEM15 conversion storage register

This group of registers are all 16-bit registers, used to store A/D conversion results. The lower 12 bits are used, and the upper 4 bits are 0 when read out.

4. ADC12MCTLx conversion storage control register (all bits can be modified only when ENC is low, and all bits are reset at POR)

There is a corresponding conversion memory control register for each conversion memory, so when the CSSTARTADD conversion memory address bit is set, ADC12MCTLx is also determined. The meaning of each bit of this register is as follows:

EOS——Sequence end control bit

0: sequence has not ended
1: last conversion in the sequence

SREF——Reference voltage source selection bit

0: Vr+=AVcc, Vr-=AVss
1: Vr+=VREF+, Vr-=AVss 2,
3: Vr+=VEREF+, Vr-=AVss
4: Vr+=AVcc, Vr-=VREF-/VEREF-
5: Vr+= VREF+, Vr-= VREF-/VEREF-
6, 7: Vr+= VEREF+, Vr-= VREF-/VEREF-

INCH——Select analog input channel

0~7: A0~A7
8: VeREF+
9: VREF-/VeREF-
10: Output of on-chip temperature sensor
11~15: (AVCC-AVSS)/2

5. ADC12IFG interrupt flag register is 16 bits, where the interrupt flag bit ADC12IFG.x corresponds to the conversion storage register ADC12MEMx. The meaning of each bit is as follows:

ADC12IFG.x is set: the conversion is completed and the conversion result has been loaded into the conversion storage register.
ADC12IFG.x is reset: ADC12MEMx is accessed.

6. ADC12IE interrupt enable register is 16 bits, corresponding to ADC12IFG register. The meaning of each bit is as follows:

ADC12IE.x = 1: Enables the interrupt request service that occurs when the corresponding interrupt flag ADC12IFG.x is set.
ADC12IE.x = 0: Disables the interrupt request service that occurs when the corresponding interrupt flag ADC12IFG.x is set.

7. ADC12IV interrupt vector register

ADC12 is a multi-source interrupt: there are 18 interrupt flags (ADC12IFG.0~ADC12IFG.15 and ADC12TOV, ADC12OV), but only one interrupt vector. Therefore, it is necessary to set the priority order of these 18 flags, and arrange the response of the interrupt flags according to the priority order. A high-priority request can interrupt the low-priority one being served. As shown in the following table:

Each interrupt flag will generate an even number from 0 to 36.

ADC12OV and ADC12TOV will automatically reset after accessing ADC12IV. However, after responding to the interrupt service corresponding to the ADC12IFG.x flag, the corresponding flag will not be automatically reset to ensure that overflow can be handled.