ARM interrupt difference - the difference between LPC2142 and S3C2440

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 *Description: Difference between ARM interrupts - Difference between LPC2142 and S3C2440
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    The difference between LPC and Samsung ARM is that Samsung has fixed the address of interrupt vector, while LPC does not.

All interrupt sources have corresponding interrupt vectors. 

• About Samsung ARM

(1) Using vector interrupts 

ENTRY

b ResetHandler                                  ;   0x00

b HandlerUndef                                  ;   0x04

b HandlerSWI                                    ;   0x08

b HandlerPabort                                 ;  0x0c

b HandlerDabort                                 ;   0x10

b .                                            ;   0x14

b HandlerIRQ                                    ;   0x18

b HandlerFIQ                                    ;   0x1c

ldrpc,=HandlerEINT0                           ;   0x20

ldrpc,=HandlerEINT1

ldrpc,=HandlerEINT2

ldrpc,=HandlerEINT3

ldrpc,=HandlerEINT4567

ldrpc,=HandlerTICK                            ;   0x34

b.

b.

ldrpc,=HandlerZDMA0                           ;   0x40

ldrpc,=HandlerZDMA1

ldrpc,=HandlerBDMA0

ldrpc,=HandlerBDMA1

ldrpc,=HandlerWDT

ldrpc,=HandlerUERR01                          ;   0x54

b.

b.

ldrpc,=HandlerTIMER0                          ;   0x60

ldrpc,=HandlerTIMER1

ldrpc,=HandlerTIMER2

ldrpc,=HandlerTIMER3

ldrpc,=HandlerTIMER4

ldrpc,=HandlerTIMER5                          ;   0x74

b.

b.

ldrpc,=HandlerURXD0                           ;   0x80

ldrpc,=HandlerURXD1

ldrpc,=HandlerIIC

ldrpc,=HandlerSIO

ldrpc,=HandlerUTXD0

ldrpc,=HandlerUTXD1                            ;   0x94

b.

b.

ldrpc,=HandlerRTC ; 0xa0

b.

b.

b.

b.

b .

b.

ldrpc,=HandlerADC                             ;   0xb4

Detailed analysis: The biggest difference is that ldr pc, = HandlerEINT0 starts differently. Samsung ARM makes proper use of these addresses to easily complete the interrupt jump.

(2) Do not use vector interrupts 

ENTRY

b ResetHandler                                 ;  for debug

b HandlerUndef ; handlerUndef

b HandlerSWI                                   ;  SWI interrupt handler

b HandlerPabort                                ;  handlerPAbort

b HandlerDabort                                ;  handlerDAbort

b .                                           ;  handlerReserved

b IsrIRQ

b HandlerFIQ

. . . . . .

IsrIRQ

sub             sp,sp,#4                       ;  reserved for PC

stmfd sp!,{r8-r9}

ldr             r9,=I_ISPR

ldr             r9,[r9]

move r8, #0x0

0               movs            r9,r9,lsr #1

bcs             %F1

add             r8,r8,#4

b %B0

1               ldr             r9,=HandleADC

add             r9,r9,r8

ldr             r9,[r9]

str             r9,[sp,#8]

ldmfd           sp!,{r8-r9,pc}

.. . . . .

HandleADC #4

HandleRTC               #       4

HandleUTXD1           #         4

HandleUTXD0           #         4

.. . . . .

HandleEINT3           #         4

HandleEINT2 # 4

HandleEINT1           #         4

HandleEINT0           #         4                              ;  0xc1(c7)fff84

Detailed analysis:

The big difference is IsrIRQ, and another difference is that IsrIRQ does not perform the sub lr,lr,#4 operation.

The reason is that there is no function call here, so lr is still

It is the value of lr saved before entering the interrupt. Because when the function is added with the __irq keyword (interrupt service function),

The compiler automatically adds the

sub lr,lr,#4

stmfd sp!,{r0-r3,r12,lr} (only pushes r0-r3,r12,lr. When the ARM kernel enters an interrupt, the default stack is r4-r7)

.....

ldmfd sp!,{r0-r3,r12,pc}^

Note: IsrIRQ is not reentrant.

; The reason why sub lr,lr,#4 does not appear here is that there is no function call here, so lr still

; is the value of lr saved before entering the interrupt. Because when the function is added with the __irq keyword (interrupt service function),

; The compiler automatically adds before executing the interrupt service function

; sub lr,lr,#4

; stmfd sp!,{r0-r3,r12,lr} (only pushes r0-r3,r12,lr. When the ARM core enters an interrupt, it pushes r4-r7 by default)

; .....

; ldmfd sp!,{r0-r3,r12,pc}^

; NOTE: IsrIRQ is not reentrant.

• About ARM on LPC

For LPC ARM, we should pay special attention to the VICVectAddr register. Why do we say that?

LDR     PC, ResetAddr

LDR     PC, UndefinedAddr

LDR     PC, SWI_Addr

LDR     PC, PrefetchAddr

LDR     PC, DataAbortAddr

DCD     0xb9205f80

LDR     PC, [PC, #-0xff0]

LDR     PC,FIQ_Addr

Detailed analysis:

    The address of LDR PC, [PC, #-0xff0] is 0x18, so what is the value pointed to by PC at this time? We can calculate it like this

PC=0x18+8-0xff0=0xfffff030, which is exactly the address of the VICVectAddr register, and VICVectAddr stores the address of the interrupt routine to be executed, because when an interrupt occurs, the hardware automatically copies the values ​​of VICVectAdd0 and VICVectAddr1 to VICVectAddr.

   Therefore, LPC can achieve interruption by setting an address similar to VICVectAdd0.