SPI initialization of stm32

1 void SPIx_Init(void)

 2 {     

 3 RCC->APB2ENR|=1<<2; //PORTA clock enable      

 4 RCC->APB2ENR|=1<<12; //SPI1 clock enable 

 5            

 6 //Here is only for SPI port initialization

 7 GPIOA->CRL&=0X000FFFFF; 

 8 GPIOA->CRL|=0XBBB00000; //PA5.6.7 multiplexed push-pull output         

 9 //GPIOA->ODR|=0X7<<5; //PA5.6.7 pull-up should not work because this mode

10 SPI1->CR1&=~(1<<6); //Turn off SPI to configure some bits

11 

12 SPI1->CR1&=~(1<<15); //1: two-line bidirectional mode 0: unidirectional bidirectional mode

13 SPI1->CR1&=~(1<<13);//1: Enable CRC check 0: Disable CRC check Can only be rewritten when SPE=0, otherwise an error will occur. Can only be used in full-duplex mode

14 SPI1->CR1|=0<<11; //1: 16-bit data format 0: 8-bit data format It can only be rewritten when SPE=0, otherwise an error will occur.

15 SPI1->CR1|=0<<10; //1: full-duplex mode 0: receive only mode    

16 SPI1->CR1|=1<<9; //1: Enable software slave device management 0: Disable software slave device management When it is 1, the NSS level is determined by the SSI bit

17 SPI1->CR1|=1<<8;//

18 SPI1->CR1|=0<<7; //1: send MSB first 0: send LSB first

19 SPI1->CR1|=0<<3 //5~3bit: frequency division coefficient 0~7 The frequency division coefficient is Fpclk/2, 4, 8, 16, 32, 64, 128, 256

20 SPI1->CR1|=1<<2; //1: master device 0: slave device 

21 SPI1->CR1|=1<<1; //CPOL 1: SCK is 1 when idle 0: SCK=0 when idle

22 SPI1->CR1|=1<<0; //CPHA 1: Data sampling starts from the second clock edge 0: Data sampling starts from the first clock edge      

23 SPI1->CR1|=1<<6; //1: turn on SPI 0: turn off SPI

twenty four }