2440 development board startup code learning

2440init.s is the main file of the startup code, including 3 header files, option.inc, memcfg.inc, and 2440addr.inc.

      option.inc defines three stack start addresses, bus width, clock related parameters, etc. The bus width will be used as an IF judgment to determine the bit width setting of each bank, see memcfg.inc file and datasheet.

      memcfg.inc is the configuration file of the memory bank, which defines the values ​​of the memory-related register bits. The bit width settings of each bank are also defined in this file. Note that there is no relevant definition for the bit width of bank0 because its bit width depends on the OM[1:0] pins, that is, the boot mode.

      2440addr.inc defines the relevant register addresses, including memory control registers, clock power management registers, interrupts, watchdogs, IO, NAND, miscellaneous and other related registers.

      2440init.s is the main startup code file, which configures important things such as memory, interrupt service routines, stacks, etc., and finally starts jumping to C code.

      The Init section is the starting point, jumping to ResetHandler. Then perform the following steps:

      Disable the watchdog, disable interrupts, disable sub-interrupts, then adjust the lock time, then set the ratio of FCLK to HCLK to PCLK to 1:2:4, then set UPLL to 48M, and after a delay of 7 clock cycles, set MPLL to 400M.

      At this time, the reset status register is read to determine whether the reset is a power-on reset, a wake-up reset, or a watchdog reset. If it is a wake-up reset, jump to the corresponding position and release SCLK, set SDRAM, return, etc.

      If it is not a wake-up reset, the SDRAM will continue to be configured. In fact, a data buffer pool named SMRDATA is sent to the relevant control registers one by one. The relevant initialization configuration is defined in the memcfg.inc file.

      Then jump to the initialization stack, which will be discussed later.

      Then read the relevant bits of the BWSCON register to determine whether it is booted from NOR or NAND. If it is NOR boot, jump to copy_proc_beg.

      This part mainly moves the RW area from the beginning of the address in the ROM to the RAM area, and then clears the ZI area behind it to 0.

      If it is NAND boot, jump to nand_boot_beg.

      First configure the timing parameters and related control functions of NAND, then jump to ReadNandID, etc. Finally, complete the RAM copying similar to the above. You will learn related content later.

      Then put the address of IsrIRQ into the address of HandleIRQ. In this way, the interrupt service routine can be found when an interrupt occurs.

      Finally, it jumps to the MAIN function and the startup code of the assembly part ends.

      The interruption content is explained in detail as follows:

      First, a macro is defined with the name "$HandlerLabel HANDLER $HandleLabel". After the macro is expanded, it becomes a code segment with $HandlerLabel as the entry name, such as "HandlerIRQ HANDLER HandleIRQ". After the macro is executed, the content at the $HandleLabel address will be executed. For example, the content at the HandleIRQ address will be executed.

      When an interrupt occurs, ARM will execute instructions from address 0x18, which is a jump instruction "b HandlerIRQ", and then execute the above macro. After the macro is executed, the content in the HandleIRQ address is executed, which is the code part with the entry name IsrIRQ. The execution function of the IsrIRQ code segment is to first read the INTOFFSET register to determine which interrupt source is, record the address offset of its interrupt service subroutine, and then add this offset to the base address, that is, the address where the entry address of the EINT0 interrupt service subroutine is located, and finally start execution from this address.

      The entry addresses of the interrupt service subroutines of all interrupts triggered by various interrupt sources are fixed, so there is a data segment starting with _ISR_STARTADDRESS after the startup code, and all address names are defined starting with Handle, such as HandleTIMER0.

      When IsrIRQ is executed, the address of the real interrupt service subroutine is found from the address of the fixed interrupt service subroutine address and executed.