MCU STC89C52RC Internal EEPROM

The data of the microcontroller when it is running is stored in RAM (Random Access Memory). The data in RAM cannot be retained after power failure. So
how to prevent the data from being lost after power failure? This requires the use of memory such as EEPROM or FLASHROM.

In traditional single-chip microcomputer systems, external memory is usually used for expansion, and data communication between the single-chip microcomputer and the memory is carried out through interfaces such as IIC or SPI.

This will not only increase the development cost, but also require more effort in program development. The STC microcontroller has a built-in EEPROM (actually,
the ISP/IAP technology is used to read and write the internal FLASH to implement the EEPROM), which saves external resources and is more convenient to use. The following
is a detailed introduction to the STC microcontroller's built-in EEPROM and its usage

The built-in EEPROM capacity of each type of STC microcontroller is as small as 2K and as large as 16K, which basically meets the needs of the project very well. What is more
convenient is that it saves peripheral EEPROM devices, achieving the purpose of saving costs, and the speed of the internal EEPROM is
much faster than the external EEPROM. The
built-in EEPROM of each type of STC microcontroller is based on 512 bytes as a sector. The starting address of EEPROM = FALSH capacity value + 1,
so the starting address of STC89C52RC is 0x2000, the starting address and end address of the first sector are 0x2000~0x21FF, the starting address and end address of the second sector are
0x2200~0x23FF, and so on for other sectors.
In-depth focus:

Traditional EEPROM is an electrically erasable programmable read-only memory chip that does not lose data after power failure.
The EEPROM of STC89C52RC is implemented by reading and writing internal FLASH through ISP/IAP technology.
The starting address of the EEPROM of STC89C52RC is 0x2000, with 512 bytes as a sector, and the size of EEPROM is 2K bytes.

There are 6 registers implemented by STC89C52RC and EEPORM, namely ISP_DATA, ISP_ADDRH, ISP_ADDRL
ISP_TRIG, ISP_CMD, and ISP_CONTR.

1. ISP_DATA registerISP_DATA
register: data register for ISP/IAP operation. ISP/IAP reads
data from Flash here, and writes data to Flash here. Example 1: Read single byte UINT8 EEPROMRead(UINT16 addr) { ……         return ISP_DATA; } Example 2: Write single byte void EEPROMWrite(UINT8 byte) { ……        ISP_DATA=byte; }

2.ISP_ADDRH, ISP_ADDRL registers
ISP_ADDRH: The high eight bits of the address register during ISP/IAP operation
ISP_ADDRL: The low eight bits of the address register during ISP/IAP operation
Example 1: Set the address
void EEPROMSetAddress(UINT16 Addr)
{
……
     ISP_ADDRH=(UINT8)(Addr>>8);
     ISP_ADDRL=(UINT8) Addr;
}

3.ISP_CMD Register
ISP_CMD: Command mode register for ISP/IAP operation, which needs to be triggered by ISP_TRIG command to take effect.

 
4.ISP_TRIG register
ISP/IAP command must be triggered by ISP_TRIG command trigger register to take effect, that is, the command set by ISP_CMD must take effect.
The triggering process is very special. You only need to assign values ​​to the ISP_TRIG register twice in a row. First write
0x46 to the ISP_TRIG register, and then write 0xB9 to complete the command triggering process.
Example 1: Command trigger
void EEPROMCmdTrig (void)
{
……
      ISP_TRIG = 0x46;
      ISP_TRIG = 0xB9;
}
 
5.ISP_CONTR register
ISP_CONTR: ISP/IAP control register

ISPEN: ISP/IAP function enable bit. 0: Disable ISP/IAP programming to change Flash.
SWBS: 0: Software selects to start from the user main program area 1: ISP program area starts
SWRST: 0: No operation 1: Generate software system reset, hardware automatically clears
WT2, WT1, WT0: Set waiting time

Assuming the operating frequency of STC89C52RC is 12MHz, the machine cycle is 1us. Referring to Table 12-, the time required for reading a single
byte is roughly as follows:
Reading a single byte: 11*1us=11us
Writing a single byte: 60*1us=60us
Sector erasing: 10942*1us=10.942ms
Regardless of the operating frequency of the microcontroller, the time required for the EEPROM read, write, and erase operations is approximately 10us, 60us, and
10ms, respectively.

In-depth focus:

There are 6 registers implemented by STC89C52RC and EEPORM, namely ISP_DATA, ISP_ADDRH,
    ISP_ADDRL ISP_TRIG, ISP_CMD, and ISP_CONTR.
The command trigger of EEPROM must first write 0x46 to the ISP_TRIG register, and then write 0xB9.
Regardless of the operating frequency of the microcontroller, the time required for the read, write, and erase operations of EEPROM is
   approximately 10us, 60us, and 10ms, respectively. Therefore, the waiting time must be set for ISP_CONTR, otherwise the data is prone to problems.