Key points of AVR microcontroller interrupt application design

AVR has many interrupt sources, especially ATmega128, which has 35 external and internal interrupt sources. Usually, the lowest position (0x0000-0x0045) of the Flash program memory space is defined as the reset and interrupt vector space. See Table 2-23 in Chapter 2 for the complete interrupt vectors. In the interrupt vector table, the interrupt corresponding to the interrupt vector at the low address has a high priority, so the system reset RESET has the highest priority.

A. Interrupt design points:

1. For AVRs with Bootloader function, the interrupt vector area can be migrated back and forth between the lowest position of Flash program memory space and the head of Bootloader area. This is mainly used to cooperate with the application of Bootloader program. If the Bootloader function is not used, the interrupt vector area should not be migrated.

2. For AVR chips with smaller Flash memory, one interrupt vector occupies one word of space, which is used to place a relative transfer RJMP instruction (range -2K~+2K words) to jump to the interrupt service routine. For unused interrupts, an interrupt return instruction RETI should be placed in the interrupt vector area to enhance the program's anti-interference ability.

3. The Flash space of ATmega128 is 64K bytes, so one of its interrupt vectors occupies 2 words of space, which is used to place an absolute transfer JMP instruction (the instruction length is 2 words) to jump to the interrupt service routine. For unused interrupts, two interrupt return instructions RETI should be placed continuously in the interrupt vector area to enhance the anti-interference ability of the program. When using assembly language to write system programs, you should pay attention to this.

4. When the MCU responds to an interrupt, its hardware system will automatically push the interrupt return address into the system stack, and turn off the global interrupt response (the hardware will clear the interrupt flag I bit to 0), and clear the interrupt flag of the interrupt; when executing the interrupt return instruction RETI, the hardware will first allow the global interrupt response (the hardware will set the interrupt flag I bit to 1), and then pop the return address from the system stack into the PC program counter, and continue to execute the program interrupted by the interrupt. In addition, the MCU hardware does not do any other processing for interrupt protection.

5. Therefore, when writing an interrupt service program, the user must first write an interrupt context protection program, such as protecting the MCU status register, etc. Do not forget to restore the interrupt context before the interrupt returns.

6. If the external interrupt response is set and enabled, even if the external INT0..7 pins are set as outputs, the level change on the pins will trigger the external interrupt. This feature provides a way to generate interrupts using software.

7. External interrupts can be triggered by rising edge, falling edge, level change (from high to low or from low to high), low level, etc. There is no external high level trigger. The specific triggering mode is determined by the external interrupt control registers EICRA (INT3:0) and EICRB (INT7:4).

8. If you choose to trigger an interrupt using an external low-level mode, you should pay special attention to the following: (1) The low level on the pin must be maintained until the current instruction is executed before the interrupt can be triggered; (2) The low-level interrupt does not set the interrupt flag, that is, the external low-level interrupt is not triggered by the interrupt flag, but directly triggers the interrupt after the level on the external pin is inverted (of course, the global interrupt enable must be enabled). Therefore, when using the low-level trigger mode, the interrupt request will be maintained until the low level on the pin disappears. In other words, as long as the input pin of the interrupt pin maintains a low level, the interrupt will be triggered. Therefore, in the low-level interrupt service program, there should be corresponding operation commands to control the external device to release or cancel the low level applied to the external pin.

B. Interrupt priority and interrupt nesting processing

1. The priority of the AVR interrupt is determined by the position of the interrupt vector in the interrupt vector area. The interrupt corresponding to the interrupt vector at a low address has a high priority, so the system reset RESET has the highest priority.

2. When two interrupts are requested at the same time, the MCU responds to the interrupt with higher priority first. The interrupt with lower priority will generally keep the interrupt flag status (except for external low-level interrupts) and wait for the MCU to respond.

3. After the MCU responds to an interrupt, the global interrupt enable bit is automatically cleared by hardware before entering the interrupt service. Therefore, even if a higher priority interrupt request occurs at this time, the MCU will not respond. It will have to wait until the RETI instruction is executed, return from this interrupt, and execute an instruction before it can continue to respond to the interrupt. Therefore, by default, AVR interrupts cannot be nested. The priority of AVR interrupts only works when multiple interrupts occur at the same time. At this time, the MCU will respond to the high-priority interrupt first.

4. AVR interrupt nesting is implemented by software. For example, in the B interrupt service, if the MCU needs to respond to the A interrupt in time (not wait until the current interrupt returns), the B interrupt service program should be designed as follows: (1) B interrupt site protection; (2) shielding interrupt enable flags other than A; (3) using instruction SEI to enable global interrupts; (4) B interrupt service; (5) using instruction CLI to disable global interrupts; (6) restoring the interrupt enable flag that was shielded in this interrupt program; (7) B interrupt site restoration; (8) B interrupt return.

5. The advantage of using software to implement nested interrupt processing is that it allows programmers to decide the importance of interrupts based on different actual situations and needs, and has more flexible means of handling interrupt responses and interrupt nesting, such as allowing low-priority interrupts (which are very important at this time) to interrupt the service of high-priority interrupts, etc. However, it also increases the complexity of writing interrupt service programs.

6. Due to the high execution speed of AVR instructions, it is generally not recommended to use the interrupt nesting method. Of course, this also requires users to follow the principle of keeping the interrupt service program as short as possible when writing the interrupt service program.

C. Writing interrupt service routines in a high-level language development environment

1. In the high-level language development environment, the corresponding methods of writing interrupt service programs are expanded and provided, but the syntax rules and processing methods of writing interrupt service programs in different high-level language development environments are different. Before writing an interrupt service program, the user should have a good understanding of the development platform used, the writing method of the interrupt program, the interrupt processing method, etc.

2. When using high-level languages ​​such as ICCAVR, CVAVR, BASCOM-AVR to write interrupt service programs, it is usually not necessary to consider the processing of interrupt context protection and recovery, because when the compiler compiles the source code of the interrupt service program, it will automatically add the corresponding interrupt context protection and recovery instructions to the generated target code.

3. If the user wants to write a more efficient or special interrupt service program, measures such as embedded assembly and automatic generation of interrupt protection and recovery code by turning off the compiler system can be adopted, but the programmer must have a deeper understanding and mastery of the development environment used and have a high level of software design ability. The USART receive and send interrupt service program (using the CVAVR development platform) given by me is a very typical example. 
 AVR Main Features      
Compiled by: Neutron     
Author: Mr. Ma Chao
Original Source: OurAVR.com Technical Forum

　　High reliability, powerful functions, high speed, low power consumption and low price have always been important indicators for measuring the performance of microcontrollers, and are also necessary conditions for microcontrollers to occupy the market and survive.

　　The early single-chip microcomputers adopted a safe solution mainly due to the low level of technology and design, high power consumption and poor anti-interference performance: using a higher frequency division coefficient to divide the clock, which makes the instruction cycle long and the execution speed slow. Although the later CMOS single-chip microcomputers adopted measures such as increasing the clock frequency and reducing the frequency division coefficient, this situation has not been completely changed (51 and 51 compatible). Although some reduced instruction set microcontrollers (RISC) have been introduced, they still follow the practice of clock division.

　　The introduction of AVR microcontrollers completely broke this old design pattern, abolished the machine cycle, abandoned the practice of complex instruction computers (CISC) to pursue complete instructions; adopted a reduced instruction set, using words as the unit of instruction length, and arranged rich operands and operation codes in one word (most of the single-cycle instructions in the instruction set are like this), with a short instruction fetch cycle, and can pre-fetch instructions to achieve pipeline operation, so instructions can be executed at high speed. Of course, this speed jump is backed by high reliability.

　　The hardware structure of AVR microcontroller adopts a compromise strategy between 8-bit and 16-bit machines, that is, a local register storage stack (32 register files) and a single high-speed input/output solution (i.e., input capture register, output comparison match register and corresponding control logic). It improves the instruction execution speed (1Mips/MHz), overcomes the bottleneck phenomenon, and enhances the function; at the same time, it reduces the cost of peripheral management, relatively simplifies the hardware structure, and reduces the cost. Therefore, AVR microcontroller has achieved an optimized balance in software/hardware cost, speed, performance and cost, and is a cost-effective microcontroller.

　　AVR microcontrollers have built-in high-quality Flash program memory, which is easy to erase and write, supports ISP and IAP, and is convenient for product debugging, development, production, and updating. The built-in long-life EEPROM can store key data for a long time to avoid power loss. The large-capacity RAM on the chip can not only meet the use of general occasions, but also more effectively support the use of high-level languages ​​to develop system programs, and can expand external RAM like the MCS-51 microcontroller.

　　All I/O lines of AVR microcontrollers have configurable pull-up resistors, can be individually set as input/output, can be set as (initial) high-impedance input, and have strong driving capabilities (power driver devices can be omitted), making the I/O port resources flexible, powerful, and fully utilized.

　　AVR microcontrollers have multiple independent clock dividers for URAT, I2C, and SPI. Among them, the pre-divider with up to 10 bits in combination with the 8/16-bit timer can provide various levels of timing by setting the frequency division coefficient through software. The unique design method of AVR microcontrollers, "using timer/counter (single) bidirectional counting to form a triangular wave, and then coordinating with the output comparison matching register to generate a variable duty cycle, variable frequency, and variable phase square wave (i.e. pulse width modulation output PWM)", is even more refreshing.

　　The enhanced high-speed synchronous/asynchronous serial port has the functions of hardware-generated check code, hardware detection and check error detection, two-level receiving buffer, automatic baud rate adjustment and positioning (when receiving), and data frame shielding, which improves the reliability of communication, facilitates program writing, and is more convenient for forming distributed networks and realizing complex applications of multi-machine communication systems. The serial port function greatly exceeds the serial port of MCS-51/96 microcontrollers. In addition, the AVR microcontroller is high-speed and the interrupt service time is short, so high baud rate communication can be achieved.

　　Byte-oriented high-speed hardware serial interface TWI, SPI. TWI is compatible with I2C interface, and has functions such as ACK signal hardware transmission and recognition, address recognition, bus arbitration, etc., and can realize multi-machine communication of all 4 combinations of master/slave receiving/transmitting. SPI supports multi-machine communication of 4 combinations such as master/slave.

　　The AVR microcontroller has an automatic power-on reset circuit, an independent watchdog circuit, a low voltage detection circuit BOD, multiple reset sources (automatic power-on and power-off reset, external reset, watchdog reset, BOD reset), and a programmable delay after startup, which enhances the reliability of the embedded system.

　　AVR microcontrollers have multiple power-saving sleep modes and can operate in a wide voltage range (5-2.7V). They have strong anti-interference capabilities and can reduce the software anti-interference design workload and hardware usage in general 8-bit machines.

　　AVR single-chip microcomputer technology embodies the integration of multiple devices (including FLASH program memory, watchdog, EEPROM, synchronous/asynchronous serial port, TWI, SPI, A/D analog-to-digital converter, timer/counter, etc.) and multiple functions (reset system for enhanced reliability, sleep mode for reduced power consumption and anti-interference, interrupt system with a wide variety of categories, timer/counter with diversified functions such as input capture and compare match output, I/O port with replacement function...), which fully reflects the development direction of single-chip microcomputer technology from "self-operating" to "system on chip SoC".

　　To sum up, the AVR microcontroller has the strengths of many others and unique technology, making it a worthy leader among 8-bit machines.