Video Data Acquisition System Based on High-Speed ​​A/D Converter

　　2 System Hardware Design

　　The amount of data collected by the video acquisition system within one image determines the image quality, which is often referred to as resolution or pixels. According to the signal characteristics of my country's PAL standard, 25 frames of images are scanned per second, and each frame of the image is divided into two odd and even fields, so the scanning time of one image is 20 ms. The vertical resolution of the cameras currently on the market, whether CCD or CMOS imaging, is basically above 400 lines. Therefore, it is deduced that the duration of a single-line video signal is less than 20 ms/400=50μs. Then, how to quickly A/D convert the video signal within 50μs to obtain more gray value data to improve the horizontal resolution becomes a key issue in the design of the video acquisition system.

　　2.1 High-speed A/D converter

　　TLC5510 is a CMOS, 8-bit high-impedance parallel analog-to-digital converter (ADC) produced by TI in the United States. It operates on a single +5 V power supply and can provide a maximum sampling rate of 20 MSPS. The full input range of TLC-551O is 2 V, and the full input range of TLC551OA is 4 V. TLC5510 uses a semi-flash structure and CMOS process, which greatly reduces the number of comparators in the device and can maintain low power consumption while converting at high speed. Under recommended operating conditions, the power consumption of TLC5510 is only 130 mW.

　　The TLC5510 analog-to-digital converter contains a clock generator, an internal reference voltage divider, a set of high 4-bit sampling comparators, an encoder, a latch, two sets of low 4-bit sampling comparators, an encoder, and a low 4-bit latch. The external clock signal CLK of the TLC5510 can generate three internal clocks through its internal clock generator to drive three sets of sampling comparators. The reference voltage divider can be used to provide reference voltages for these three sets of comparators. The high 4 bits of the output A/D signal are directly provided by the high 4-bit encoder, while the low 4-bit sampling data are alternately provided by two low 4-bit encoders. The working sequence of TLC551O is shown in Figure 2. The clock signal CLK collects the analog input signal at each falling edge. The data collected for the Nth time is sent to the internal data bus after a delay of 2.5 clock cycles. At this time, if the output enable terminal OE is valid, the data can be sent to the 8-bit data bus.

　　
Figure II

　　TLC5510 not only has high-speed A/D conversion function, but also has internal sampling and holding circuit, which greatly simplifies the design of peripheral circuits. Only the internal reference resistor and VDDA are needed to form a reference voltage divider to achieve a full-scale conversion range of 2V. Because the maximum voltage value of a normal composite video signal does not exceed 2V, in the design of this system, the REF-BS terminal of TLC5510 is short-circuited to the REFB terminal, and the REFTS terminal is short-circuited to the REFT terminal to obtain a 2V reference voltage. The video signal is input from the ANALOGIN pin, and a 4MHz active crystal oscillator is used to provide a clock signal. Through calculation, it can be seen that the chip can perform 200 A/D conversions within the scanning time of a single-line video signal. For simple image algorithms, the horizontal resolution can fully meet the requirements. If the working clock frequency of TLC5510 is increased, the horizontal resolution can be further improved. If TLC5510 is operated under extreme conditions (sampling rate of 20 MHz), the horizontal resolution can reach about 800 points, that is, more than 300,000 pixels. After power-on, since the OE pin of TLC5510 is connected to GND, the chip is always in a low active state, so the A/D conversion will continue to work. The 8-bit data output is directly connected to the input of the next level FIFO memory, and the processor decides whether the memory will write the A/D conversion data.

　　The specific application circuit is shown in Figure 3. It should be noted that because the AGND pin and DGND pin of TLC5510 are not connected internally, they need to be connected externally. It is recommended to use an inductor or a magnetic bead connection to remove the noise of the analog ground to the digital signal. At the same time, between the VDDA and AGND, VDDD and DGND pins, a 0.1 μF capacitor should be used for decoupling. It is recommended to use a ceramic capacitor and a tantalum capacitor of more than 10 μF for energy storage.

　　
Figure 3

　　2.2 FIFO Memory

　　uPD42280 is a 2 Mbit dual-port FIFO (first-in, first-out) memory. In this system, it is used as a cache for A/D conversion data. It has a large capacity and high cost-effectiveness, and can meet the storage requirements of about 250,000 pixels of one frame of image data. A/D conversion data is written or read out in a certain clock beat sequence, and its read and write clock rate can reach up to 33 MHz. The data of uPD42280 itself is 8-bit parallel input and output. The data is written and read by controlling the level of its WE pin, WRST pin, RE pin and RRST pin. Figure 4 shows the read and write cycle timing of uPD42280.

　　
Figure 4

　　In the write control cycle, if WE is in the low active state (WRST is high at this time), the data is written to the memory address before the rising edge of the next cycle arrives; if WE is in the high disabled state, writing is suspended and the write address pointer is maintained. When WE is in the low active state, if WRST is at a low level, the write address pointer will return from the current address to address 0. After WRST returns to a high level, data will also be written from address 0. In the read control cycle, if RE is in the low active state (RRST is high at this time), the data will be read when the rising edge of the next cycle arrives; if RE is in the high disabled state, reading is suspended and the read address pointer is maintained. When RE is in the low active state, if RRST is at a low level, the read address pointer will return from the current address to address 0. After RRST returns to a high level, data will also be read from address 0.

　　In this system, the read and write clock of uPD42280 and the working clock of TLC5510 use the same signal source (4 MHz), which not only ensures the synchronization of FIFO write operation and A/D conversion operation, avoiding data leakage or mixing, but also makes the reading rate determined only by the reading time of the processor IO port when reading data. By controlling the read and write enable signals and the read and write address reset signals through the processor IO port, the reading, writing and updating of a frame of image data can be completed. When the bus frequency of the processor is 32 MHz, within the scanning time of a single-line video signal (about 50 us), the IO port can finally read the grayscale values ​​of about 190 valid pixels. Excluding the points that need to be omitted in the line blanking area and the center of the image, the effective pixel points that can be collected by this system for each line of video signal are 160.

　　It should be noted that the peripheral circuit of uPD42280 itself is very simple, and only one decoupling capacitor needs to be added between the power supply and the ground. However, since FIFO memory is different from RAM, it cannot perform internal addressing operations, and can only perform simple address reset. Therefore, when controlling the software, you must pay attention to the logic and strictly control the 4 pins according to the read and write timing to ensure the complete writing and reading of an image.

　　The innovation of this system is to use the high-speed A/D converter TLC5510 and the FIFO memory uPD42280 together to realize the conversion and data storage of video signals. This makes the conversion and storage of the entire front end completely controlled by several IO ports, with low performance requirements and resource requirements for the microcontroller itself, and only uses the two-way interrupt and multiple ordinary IO ports of the microcontroller. This design makes the system highly portable and can be used for a variety of microcontrollers or DSPs. In addition, these two core devices are 8-bit parallel data input and output, which are very fast and can achieve high-speed transmission of video data.
 

　　3 Software Process

　　The software part mainly includes initialization, write operation, read operation and image processing. First, initialize the processor's IO port and interrupt port, PORTB8 bit as data entry, input enable; PORTK0~PORTK3 as memory read and write enable and address control line, output enable, PORTJ0 and PORTJ1 respond to line and field interrupt respectively, rising edge trigger.

　　The main function is an infinite loop, which continuously detects whether the image acquisition is completed. If the acquisition is completed, the image processing is performed, and then the corresponding control output is made. The main function of the field interrupt service function is to clear the row counter and write the address back to zero to prepare for a new frame of image. The main function of the line interrupt service function is to self-increase the row counter to determine the current number of rows in the image. Determine whether the acquisition has started, control the write enable, determine whether the acquisition has ended, control the write disable, control the read address back to zero, read enable, pass the data through the first-level buffer, read it into the two-dimensional array of the microcontroller through the 8-bit data bus, and notify the main function that the image data is ready. The specific process is shown in Figure 5.

　　
Figure 5

　　4 Experimental data

　　The experimental environment is a model runway with a white background and black lines. The actual collection pixel points of an image data are 160 x 20 lines. The image processing algorithm is mainly edge detection and linear interpolation, the purpose is to obtain the center line trajectory of the runway. Figure 6 shows a single line of A/D conversion data, where high grayscale values ​​correspond to white boards, low grayscale values ​​correspond to black lines, and the horizontal axis is the proportional coordinate of each sampling point on the X axis in the actual image, and the dimension is 1.

　　Figure 7 shows the recognition of different road types by the system. The upper part is the actual image captured by the camera, and the lower part is the centerline trajectory obtained after edge detection and linear interpolation of the image data. The horizontal coordinate is the proportional coordinate of the X-axis of each row of centerlines in the actual image, and the vertical coordinate is the proportional coordinate of the Y-axis of each row of centerlines in the actual image, with a dimension of 1. The horizontal and vertical coordinates can be calibrated by actual measurement of the image to obtain the two-dimensional coordinates in the real world. The corresponding values ​​are then stored in a static two-dimensional array of the microcontroller, and can be extracted and used by table lookup when needed; they can also be calculated based on the changes in the three-dimensional coordinates.

　　
Figure 7

　　It can be seen that the track of the centerline of the runway is in good agreement with the actual image. The track of the curve can well reflect the characteristics of the runway, making it easier to determine the type of runway, providing reliable information for the next control strategy.

　　5 Conclusion

　　This paper proposes a video acquisition system based on high-speed A/D converter TLC5510 and FIFO memory uPD42102, which provides a new idea for ordinary single-chip microcomputers to achieve high-speed and high-precision acquisition of video signals. The system circuit is simple and stable, with strong portability and low requirements on microprocessors. It can be applied to the acquisition of composite video signals output by most CCD or CMOS cameras. Experiments have proved that the system can provide a reliable front-end hardware platform for image processing.