MSP430 reset signal POR and PUC

There are two reset signals for MSP430: power-on reset signal (POR) and power-on clear signal (PUC). There are also signals that can trigger POR and PUC: 5 from the watchdog, 1 from the reset pin, and 1 from the signal generated by an error in writing the FLASH key value.
The POR signal only occurs in 2 situations:

(1) The microprocessor is powered on;

(2) The system is reset when a low level is generated on the RST/NMI pin.
Conditions for generating the PUC signal:

(1) POR signal generation;

(2) When the watchdog is valid, the watchdog timer overflows;

(3) An error occurred while writing the watchdog timer security key value;

(4) An error occurred while writing the FLASH memory security key value.

The relationship between POR and PUC: The generation of POR signal will cause the system to reset and generate PUC signal. However, PUC signal will not cause the generation of POR signal.
           Whether it is a reset triggered by POR signal or PUC signal, MSP430 will read the reset interrupt vector from address 0xFFFE, and the program will start to execute from the address pointed to by the interrupt vector. Among the conditions for triggering PUC signal, in addition to POR generating a triggering PUC signal, other conditions can be used to determine the cause of the PUC signal by reading the corresponding interrupt vector so as to make corresponding processing.
The status after system reset (referring to POR) is:

(1) The RST/NMI pin function is set to reset function;

(2) All I/O pins are set as inputs;

(3) The peripheral modules are initialized and their register values ​​are the default values ​​in the relevant manuals;

(4) The status register SR is reset;

(5) The watchdog is activated and enters working mode;

(6) The program counter PC is loaded with the address at 0xFFFE, and the microprocessor starts executing the program from this address.
There are three typical reset circuits:

(1) Connect a 100K ohm pull-up resistor to the RST/NMI pin.

(2) Add a 0.1uf capacitor to (1) and ground one end of the capacitor to make the reset more reliable.

(3) Based on (2), a diode of model IN4008 is connected in parallel with the resistor, which can reliably realize the system power-on immediately after power failure.

BOR 

In chips without BOR, if the power-on of the chip is periodic, the power-off VCC must be reduced to Vmin to ensure that a new POR signal occurs when VCC is loaded again. If VCC does not drop below Vmin in a cycle, or because of interference, the POR signal will not occur, so the initial state after power-on will be incorrect.
        For modules with BOR, it should be "When VCC exceeds Vcc(start), the POR signal becomes valid until VCC exceeds V(B_IT+), and then after a delay t(BOR). The delay t(BOR) will be extended accordingly as the angle of the Vcc voltage increases. The hysteresis
Vhys(B_IT-) requires VCC to drop below V(B_IT-) to ensure that the POR signal is generated again through the BOR circuit. V(B_IT-) is higher than Vmin, which enables BOR to provide a valid power failure restart signal when VCC does not drop to Vmin.

        Battery replacement in high-precision devices can cause voltage fluctuations. The zero-power brownout reset (BOR) function is used to reset the MSP430 in low-voltage conditions to prevent unexpected device behavior.