Active low power-on reset timer (1s POR) - timer circuit diagram

　　The LTC6995 provides a simple, accurate, low-frequency clock that is uniquely configured for long-duration power-on reset and watchdog timer applications. In this example, the LTC6995 integrates a programmable oscillator with high-precision circuitry and logic to achieve an accurate 1s POR. The resistor-settable POR can be programmed for a period from 1ms to 4.8 hours. Once a power-up or reset signal is received, the LTC6995 will initiate a complete output clock cycle, and the polarity of the output is configurable for active-low or active-high operation. The LTC6995 operates under high acceleration, vibration and extreme temperature conditions and does not require timing capacitors, crystals, microcontrollers or programming.

　　Circuit functions and advantages

　　Many applications require high-resolution, differential input ADCs to convert single-ended analog signals, whether bipolar or unipolar. This DC coupling circuit can convert a single-ended input signal into a differential signal and is suitable for driving the 18-bit, 1 MSPS device AD7982 in the PulSAR series ADC. Using the ADA4941-1 single-ended to differential driver and the ADR435 ultralow-noise 5.0 V reference, this circuit can accept many types of single-ended input signals, including bipolar or unipolar signals in the high-voltage to low-voltage range.

　　Direct coupling remains throughout the circuit. If board space is a major concern, small package products can be used. All ICs shown in Figure 1 are available in 3 mm 3 mm LFCSP or 3 mm 5 mm MSOP small packages.

　　Figure 1: Single-ended to differential DC-coupled driver circuit (schematic diagram)

　　Circuit description

　　The differential input voltage range of the AD7982 is set by the voltage on the REF pin. When VREF = 5 V, the differential input voltage range is ±VREF = ±5 V. The voltage gain (or attenuation) from the single-ended source VIN to OUTP of the ADA4941-1 is set by the ratio of R2 to R1. The ratio of R2 to R1 should be equal to the ratio of VREF to the peak-to-peak input voltage VIN. When the single-ended input voltage is 10 V peak-to-peak and VREF = 5 V, the ratio of R2 to R1 should be 0.5. The signal on OUTN is the inversion of the OUTP signal. The absolute value of R1 determines the input impedance of the circuit. The feedback capacitor CF is selected based on the required signal bandwidth, which is approximately 1/(2πR2CF). The 20 Ω resistor and 2.7 nF capacitor form a 3 MHz single-pole low-pass noise filter. Resistors R3 and R4 set the IN of the AD7982? Common mode voltage at the input.

　　This common-mode voltage value is equal to VOFFSET2 &TImes; (1 + R2/R1), where VOFFSET2 = VREF &TImes; R3/(R3 + R4). Resistors R5 and R6 set the common-mode voltage at the IN+ input of the ADC. This voltage is equal to VOFFSET1 = VREF × R5/(R5 + R6). The common mode voltage of the ADC (equal to VOFFSET1) should be close to VREF/2, which means R5 = R6. Table 1 lists some standard 1% allowable resistor values ​​for common input voltage ranges.

　　Table 1: Circuit values ​​and voltages for common input voltage ranges

　　Please note that the ADA4941-1 operates with +7 V and? Powered by 2 V power supply. Since each output must swing from 0 V to +5 V, the positive supply voltage should be several hundred millivolts above +5 V, and the negative supply voltage should be several hundred millivolts below 0 V. This circuit selects +7 V and? 2 V supply voltage. The +7 V supply also provides enough headroom to power the ADR435. Other voltages can be used as long as the absolute maximum total supply voltage on the ADA4941-1 does not exceed 12 V and the headroom requirements of the ADR435 are met.

　　The AD7982 requires a +2.5 V supply for VDD as well as a VIO supply (not shown in Figure 1), which can range from 1.8 V to 5 V, depending on the I/O logic interface levels.

　　This circuit is not sensitive to power supply timing. The AD7982 input can withstand currents up to ±130 mA during transient overvoltage conditions.

　　The AD7982 SPI-compatible serial interface (not shown in Figure 1) enables daisy-chaining of several ADCs onto a single three-wire bus using the SDI input and provides an optional busy-busy indication. The device is compatible with 1.8V, 2.5V, 3V and 5V logic when using independent power supply VIO.

　　In order to achieve the desired performance of the circuits discussed in this article, excellent routing, grounding, and decoupling techniques must be used. At least a four-layer PCB should be used: one ground layer, one power layer, and two signal layers.

　　All IC power supply pins must be decoupled from the ground plane with 0.01 μF to 0.1 μF low-inductance, multilayer ceramic capacitors (MLCCs) (not shown in Figure 1 for simplicity) and should follow the guidelines cited in the "Learn More Information" section Recommendations given in the respective data sheets of the IC.

　　The product evaluation board should be consulted for recommended routing and key component locations. Check on the device's product home page (see the "Learn More Information" section).

　　Common changes

　　The ADR43x family of voltage references can provide a variety of different reference voltage values ​​for interfacing with ADCs.