STM32 NVIC interrupt priority management

The CM3 core supports 256 interrupts, including 16 core interrupts and 240 external interrupts, and has 256 levels of programmable interrupt settings. However, the STM32 does not use all of the CM3 core, but only uses part of it. The STM32 has 84 interrupts, including 16 core interrupts and 68 maskable interrupts, with 16 levels of programmable interrupt priority. We often use these 68 maskable interrupts, but the STM32 has only 60 of the 68 maskable interrupts on the STM32F103 series (68 on the 107 series).

In MDK, MDK defines the following structure for registers related to NVIC:

The interrupts of STM32 are executed in order under the control of these registers. Only by understanding these interrupt registers can we understand the interrupts of STM32. The following is a brief introduction to these registers:

ISER[2]: ISER stands for Interrupt Set-Enable Registers, which is an interrupt enable register group. As mentioned above, the STM32F103 has only 60 maskable interrupts. Here, two 32-bit registers are used, which can represent a total of 64 interrupts. However, the STM32F103 only uses the first 60 bits. Bits 0 to 31 of ISER[0] correspond to interrupts 0 to 31 respectively. Bits 0 to 27 of ISER[1] correspond to interrupts 32 to 59; in this way, a total of 60 interrupts are corresponding. If you want to enable an interrupt, you must set the corresponding ISER bit to 1 to enable the interrupt (this is just enabling, and it must be combined with interrupt grouping, masking, IO port mapping and other settings to be considered a complete interrupt setting). For specific interrupts corresponding to each bit, please refer to line 36 in stm32f10x_nvic..h.

ICER[2]: The full name is Interrupt Clear-Enable Registers, which is an interrupt disable register group. This register group has the opposite function to ISER, and is used to clear the enable of a certain interrupt. The function of its corresponding bit is the same as ICER. Here, we need to set a special ICER to clear the interrupt bit instead of writing 0 to ISER, because these registers of NVIC are valid when writing 1, and invalid when writing 0.

ISPR[2]: The full name is Interrupt Set-Pending Registers, which is an interrupt pending control register group. The interrupt corresponding to each bit is the same as ISER. By setting 1, the ongoing interrupt can be suspended and the interrupt of the same level or higher level can be executed. Writing 0 is invalid.

ICPR[2]: The full name is Interrupt Clear-Pending Registers, which is an interrupt clear control register group. Its function is opposite to ISPR, and the corresponding bits are the same as ISER. By setting 1, the pending interrupt can be cleared. Writing 0 has no effect.

IABR[2]: The full name is Interrupt Active Bit Registers, which is an interrupt activation flag register group. This is a read-only register that can be used to determine which interrupt is currently being executed. It is automatically cleared by hardware after the interrupt is executed. The interrupt represented by the corresponding bit is the same as ISER. If it is 1, it means that the interrupt corresponding to the bit is being executed.

IPR[15]: The full name is Interrupt Priority Registers, which is a register group for interrupt priority control. This register group is very important! The interrupt grouping of STM32 is closely related to this register group. Since STM32 has more than 60 interrupts, STM32 uses interrupt grouping to determine the interrupt priority. The IPR register group consists of 15 32-bit registers, and each maskable interrupt occupies 8 bits, so a total of 15*4=60 maskable interrupts can be represented. This is exactly the same as the number of maskable interrupts of STM32. IPR[0]'s [31~24], [23~16], [15~8], and [7~0] correspond to interrupts 3~0, and so on, corresponding to a total of 60 external interrupts. However, not all of the 8 bits occupied by each maskable interrupt are used, but only the upper 4 bits are used. These 4 bits are divided into preemption priority and sub-priority. The preemption priority is in front, and the sub-priority is in the back. The number of bits each of these two priorities occupies is determined by the interrupt grouping settings in SCB->AIRCR.

Here is a brief introduction to the interrupt grouping of STM32: STM32 divides interrupts into 5 groups, group 0 to 4. The setting of this grouping is defined by bits 10 to 8 of the SCB->AIRCR register. The specific allocation relationship is shown in the table

Through this table, we can clearly see the configuration relationship corresponding to groups 0~4. For example, if group is set to 3, then for all 60 interrupts, the highest 3 bits of the upper 4 bits of the interrupt priority register of each interrupt are the preemption priority, and the lower 1 bit is the response priority. For each interrupt, you can set the preemption priority to 0~7 and the response priority to 1 or 0. The preemption priority is higher than the response priority. The smaller the value, the higher the priority.

There are two points to note here: first, if the preemption priority and response priority of two interrupts are the same, the interrupt that occurs first will be executed first; second, the preemption priority with a higher priority can interrupt the ongoing interrupt with a lower preemption priority. For interrupts with the same preemption priority, the response priority with a higher priority cannot interrupt the interrupt with a lower response priority.

 

Using library functions to implement the above interrupt grouping settings and interrupt priority management simplifies our future interrupt settings. The NVIC interrupt management function is mainly in the misc.c file.

The first is the interrupt priority grouping function NVIC_PriorityGroupConfig. This function is used to group the interrupt priorities. This function can only be called once in the system. Once the grouping is determined, it is best not to change it.

For example, if we set the interrupt priority group value of the entire system to 2 (2-bit preemption priority, 2-bit response priority), the method is: NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);

After setting up the system interrupt grouping, how do we determine the preemption priority and response priority for each interrupt? Let's look at an important function, the interrupt initialization function NVIC_Init, whose function declaration is:

void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)

NVIC_InitTypeDef is a structure. You can look at the member variables of the structure:

For example, if we want to enable the interrupt of serial port 1, and set the preemption priority to 1 and the sub-priority to 2, the initialization method is: