Understanding STM32 input and output modes

(1) GPIO_Mode_AIN analog input 
(2) GPIO_Mode_IN_FLOATING floating input
(3) GPIO_Mode_IPD pull-down input
(4) GPIO_Mode_IPU pull-up input
(5) GPIO_Mode_Out_OD open-drain output
(6) GPIO_Mode_Out_PP push-pull output
(7) GPIO_Mode_AF_OD multiplexed open-drain output
(8) GPIO_Mode_AF_PP multiplexed push-pull output

For beginners, I think these concepts must be understood. The three most commonly used are push-pull output, open-drain output, and pull-up input, but I have never summarized them. Therefore, here is a summary:

Push-pull output: can output high and low levels, connect digital devices; push-pull structure generally refers to two transistors controlled by two complementary signals, always one transistor is turned on while the other is turned off. The high and low levels are determined by the power supply of the IC.

The push-pull circuit is a circuit in which two transistors or MOSFETs with the same parameters exist in the circuit in a push-pull manner, each responsible for the waveform amplification task of the positive and negative half cycles. When the circuit is working, only one of the two symmetrical power switch tubes is turned on at a time, so the conduction loss is small and the efficiency is high. The output can both inject current into the load and extract current from the load. The push-pull output stage not only improves the load capacity of the circuit, but also increases the switching speed.

Detailed understanding:

As shown in the figure, the output stage of the push-pull amplifier has two "arms" (two groups of amplifying elements). When the current of one "arm" increases, the current of the other "arm" decreases, and the states of the two are switched in turn. For the load, it seems that one "arm" is pushing and the other "arm" is pulling, and they jointly complete the current output task. When the output is high, that is, when the lower load gate inputs a high level, the current at the output end will be pulled out from the power supply of this level by the lower gate through VT3. In this way, when the output is high or low, VT3 and VT5 will work alternately, thereby reducing power consumption and improving the bearing capacity of each tube. In addition, no matter which way is taken, the on-resistance of the tube is very small, so the RC constant is very small and the conversion speed is very fast. Therefore, the push-pull output stage not only improves the load capacity of the circuit, but also improves the switching speed.

Open drain output: The output terminal is equivalent to the collector of the transistor. A pull-up resistor is required to obtain a high level state. It is suitable for current-type driving and has a relatively strong ability to absorb current (generally within 20ma).

The open-drain circuit has the following characteristics:

1. Use the driving capability of the external circuit to reduce the internal driving of the IC. When the internal MOSFET of the IC is turned on, the driving current flows from the external VCC through R pull-up, MOSFET to GND. Only a very low gate driving current is required inside the IC.

2. Generally speaking, open drain is used to connect devices of different levels and match the levels. Because when the open drain pin is not connected to an external pull-up resistor, it can only output a low level. If you need to have the function of outputting a high level at the same time, you need to connect a pull-up resistor. A good advantage is that by changing the voltage of the pull-up power supply, you can change the transmission level. For example, adding a pull-up resistor can provide TTL/CMOS level output, etc. (The resistance value of the pull-up resistor determines the speed of the edge of the logic level conversion. The larger the resistance value, the lower the speed and the lower the power consumption, so the selection of the load resistor should take into account both power consumption and speed.)

3. OPEN-DRAIN provides a flexible output mode, but it also has its weakness, which is the delay of the rising edge. Because the rising edge charges the load through an external pull-up passive resistor, when the resistor is small, the delay is small, but the power consumption is large; on the contrary, the delay is large and the power consumption is small. Therefore, if there is a requirement for delay, it is recommended to use the falling edge output.

4. Multiple open-drain output pins can be connected to one line. Through a pull-up resistor, an "AND logic" relationship is formed without adding any devices. This is also the principle of I2C, SMBus and other buses to determine the bus occupancy status. Supplement: What is "Line AND"? :

On a node (line), connect a pull-up resistor to the power supply VCC or VDD and the collector C or drain D of n NPN or NMOS transistors. The emitters E or sources S of these transistors are connected to the ground line. As long as one transistor is saturated, the node (line) will be pulled to the ground level. Because the base of these transistors injects current (NPN) or the gate adds a high level (NMOS), the transistor will be saturated, so the relationship between these bases or gates to this node (line) is NOR logic. If an inverter is added after this node, it is OR logic.

In fact, it can be simply understood as: when all the pins are connected together, an external pull-up resistor is connected. If one pin outputs a logic 0, it is equivalent to being grounded, and the loop in parallel with it is "equivalent to being short-circuited by a wire", so the logic level of the external circuit is 0. Only when all are high levels, the result is a logic 1.

Regarding push-pull output and open-drain output, we can finally summarize them with the simplest diagram:

The left side of the figure is the push-pull output mode, in which the lower PNP transistor is cut off when the comparator outputs a high level, while the upper NPN transistor is turned on, and the output level is VS+; when the comparator outputs a low level, it is just the opposite, the PNP transistor is turned on, the output is connected to the ground, and it is a low level. The right side can be understood as an open-drain output form, which needs to be pulled up.

Floating input: I have not found a very authoritative explanation for floating input, so I can only understand it from the following picture.

Since floating input is generally used for external button input, combined with the input circuit in the figure, I understand that in the floating input state, the level state of IO is uncertain and is completely determined by the external input. If the pin is left floating, the level of the port is uncertain.

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1. GPIO mode configuration

1. Input/output mode (refer to stm32 manual)

2. The difference between several speeds in GPIO output mode:

(1). GPIO pin speed: GPIO_Speed_2MHz (10MHz, 50MHz);

Also known as the response speed of the output drive circuit: (The chip has multiple output drive circuits with different response speeds arranged in the output part of the I/O port. Users can choose the appropriate drive circuit according to their needs, and choose different output drive modules by selecting the speed to achieve the best noise control and reduce power consumption.)

It can be understood as: The bandwidth of the output drive circuit: that is, the maximum frequency of the signal that a drive circuit can pass without distortion.

(If the frequency of a signal exceeds the response speed of the driving circuit, the signal may be distorted. Distortion factor?)

If the signal frequency is 10MHz and you configure a 2MHz bandwidth, the 10MHz square wave is likely to become a sine wave. It is like the design speed of a highway. When the speed of a car is lower than the design speed, it can run smoothly. If it exceeds the design speed, it will be bumpy or even overturned.

The key is: the GPIO pin speed matches the application. The higher the speed configuration, the greater the noise and the greater the power consumption.

Drivers with high bandwidth speeds consume more power and make more noise, while drivers with low bandwidth consume less power and make less noise. Using the right driver can reduce power consumption and noise

For example: high-frequency drive circuits also have high noise. When high output frequency is not required, please choose a low-frequency drive circuit, which is very helpful to improve the EMI performance of the system. Of course, if you want to output a higher frequency signal, but choose a lower frequency drive module, you may get a distorted output signal. The key is to match the GPIO pin speed with the application (recommended more than 10 times?).

for example:

① For USART serial port, if the maximum baud rate is only 115.2k, then 2M speed is enough, which saves power and reduces noise.

② For the I2C interface, if you use a 400k baud rate and want to leave more margin, you can choose a 10M GPIO pin speed.

③ SPI interface, if using 18M or 9M baud rate, you need to select 50M GPIO pin speed.

(2) The GPIO flip speed refers to the speed at which the 0 and 1 values ​​of the input/output register are reflected to the high and low levels of the external pin (APB2). The manual states that the maximum GPIO flip speed can reach 18MHz.

@Through a simple program test, the flip time observed with an oscilloscope: is a comprehensive time, including the time to fetch instructions, the time to execute instructions, the time for the signal to be transferred to the register after the instruction is executed (this may go through many links, such as AHB, APB, bus arbitration, etc.), and finally the time it takes for the signal to be transmitted from the register to the pin.

For example: if there is a pull-up resistor, the larger its resistance value, the greater the RC delay, that is, the slower the logic level conversion speed and the greater the power consumption.

(3).GPIO output speed: It is related to the program (how long it takes to output a signal as written in the program).

2. When the GPIO port is set to input, the output drive circuit is disconnected from the port, so the output speed configuration is meaningless.

3. During reset and just after reset, the multiplexing function is not enabled and the I/O port is configured in floating input mode.

4. All ports have external interrupt capability. In order to use the external interrupt line, the port must be configured in input mode.

5. The configuration of the GPIO port has a locking function. After the GPIO port is configured, the configuration combination can be locked through the program until the next chip reset.

General Applications:

ANALOGINPUT_AIN -- Apply ADC analog input, or save power in low power mode.

Floating input_IN_FLOATING——Can be used for KEY recognition, RX1

Open drain output_Out_OD——applied to I2C bus; (STM32 open drain output can only output 0 if no external pull-up resistor is connected)

2. Pin multiplexing function remapping

1. Multiplexing function: built-in peripherals share the same pins with I/O ports (different functions correspond to the same pin)

The external pins of all built-in peripherals of STM32 are multiplexed with standard GPIO pins. If there are multiple multiplexed function modules corresponding to the same pin, only one of them can be enabled, and the other modules remain disabled.

2. Remapping function: The lead-out pins of the multiplexed function can be led out from different I/O pins through remapping, that is, the lead-out pins of the multiplexed function can be changed to other pins through the program!

Direct benefit: PCB designers do not have to route certain signals around the board to complete the connection when necessary, which facilitates PCB design and potentially reduces signal cross-interference.

For example: USART1: 0: No re-imaging (TX/PA9, RX/PA10); 1: Re-imaging (TX/PB6, RX/PB7).

(Refer to the AFIO_MAPR register introduction) [0,1 is the bit value of a register]

【Note】 The following multiplexed function pins have remapping function:

- The crystal oscillator pins can be used as normal I/O ports when no crystal is connected

- CAN module; - JTAG debugging interface; - Most timer output interfaces; - Most USART output interfaces

- I2C1 lead-out interface; - SPI1 lead-out interface;

For example: for STM32F103VBT6, pin 47 is PB10, and its multiplexed functions are I2C2_SCL and USART3_TX, which means that after power-on, its default function is PB10, and I2C2's SCL and USART3's TX are its multiplexed functions; in addition, after TIM2's pin remapping, TIM2_CH3 also becomes the multiplexed function of this pin.

(1) To use the USART3 function on pins 47 and 48 of the STM32F103VBT6, you need to configure pin 47 as a multiplexed push-pull output or multiplexed open-drain output, configure pin 48 as an input mode, enable USART3 and keep I2C2 disabled.

(2) If pin 47 of STM32F103VBT6 is used as TIM2_CH3, TIM2 needs to be remapped and then the corresponding pins need to be configured in a multiplexed function manner.

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Fast switching of input and output

#define HD7279_DAT_OUT GPIOB->CRH=(GPIOB->CRH&(~(0x0000000F<<20)))|0x00000003<<20 //Push-pull output #define HD7279_DAT_IN GPIOB-
>CRH=(GPIOB->CRH&(~(0x0000000F<<20)))|0x00000004<<20 //Floating input