Understanding of SPI_NSS of STM32 series

I was also confused about SPI's NSS before. I saw in other manuals that NSS is the chip select signal. The chip select of most SPI slaves is valid at low level. When the NSS pin of a slave is low, the machine is selected and can communicate with the host through SPI. All masters and slaves actually have chip select signals, and they can only work if the chip is selected. However, the chip select of the master is completed through software configuration. I hope that it will be clear to you after reading the following paragraphs.

In STM32, when you want to configure it as a slave, just configure its NSS pin to low level. If you want to configure SPI as a master, you also need to configure this NSS, but this time configure it to SPI_NSS_Soft. What are SPI_NSS_Soft and SPI_NSS_Hard? Let's take a look at the description in the data sheet: In the spi.h file of stm32, it is defined as follows

#define SPI_NSS_Soft                    ((uint16_t)0x0200)
#define SPI_NSS_Hard                    ((uint16_t)0x0000)

It corresponds to the 9th bit (starting from the 0th bit) SSM (Software slave management) of the SPI control register. The data sheet says that when SSM is 1, the input of the NSS pin is replaced by the SSI (8th bit of empty register 1) value; when it is 0, it corresponds to the state of the external NSS pin.

 

Let's take a look at configuring the master:

#define SPI_Mode_Master                 ((uint16_t)0x0104)
#define SPI_Mode_Slave                  ((uint16_t)0x0000)

From #define SPI_Mode_Master ((uint16_t)0x0104), we can see that the 2nd bit is configured to 1 and the 8th bit is configured to 1. In the SPI control register, the 2nd bit is MSTR. When this bit is configured to 0, the SPI is configured to slave mode. If this bit is 1, it is configured to master mode. The 8th bit is SSI (internal slave selection bit). The data sheet states that only when the SSM bit is 1, the value of the SSI bit is forced to correspond to the NSS pin, and the value of the NSS pin I/O register is ignored. When SSI is 1, the corresponding NSS pin is 1. From its internal point of view, it is enabled and configured as a master.

Maybe you are a little confused, what is NSS pin and what is NSS pin I/O? My understanding is that NSS pin is one of the signal lines of SPI communication, which can be connected to the real I/O port unnecessarily and can be set and reset by software; while NSS pin I/O is the external I/O port connected to the NSS signal line. For example, as mentioned in the third paragraph above, the input of NSS pin is replaced by the value of SSI.