stm32 USART serial communication operation register + library function-EEWORLD

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Although serial communication is used less and less in today's computers because its communication speed and distance are no longer suitable for PC requirements, it has been replaced by USB port. However, USART is still widely used in the embedded field.

STM32 can provide up to 5 serial ports, with fractional baud rate generator, support for synchronous single-line communication and half-duplex single-line communication, DMA, etc. When using USART, the I/O port of STM32 is connected to the serial port of the computer through the RS232 level conversion circuit.

To use the serial port, you only need to start the serial port clock, set the corresponding I/O port mode, and configure the baud rate, data bit length, parity bit and other information before you can use it.

I used three ways to use serial communication, and only one can be enabled:

USART sends information by using the printf() function;
USART communicates with the host computer and outputs the original data after receiving it;
USART actively sends data.

Operation Register

The serial port is reset by configuring the 14th bit of the APB2RSTR register. When a peripheral fails, it can be reset through the reset register. When the system is initialized, a reset operation is performed.

The baud rate setting of the serial port is in the USART_BRR register. In fact, this register configures the value of the baud rate division trigger factor. The baud rate is the number of characters passing through in one second, and the baud rate is the number of binary bits passing through in one second. Therefore, setting the baud rate requires a period of algorithm processing to obtain the clock division value that achieves this baud rate under a specific clock.

There are three serial port control registers USART_CR1~3, and the most commonly used one is USART_CR1. The descriptions of each register are as follows:

stm32 USART serial communication operation register + library function

UE：USART enable

M: Word length This bit defines the length of the data word, 0: one start bit, 8 data bits, n stop bits;

1: One start bit, 9 data bits, n stop bits. n is set by USART_CR2.

WAKE: Wakeup method 0: Wake up by idle bus; 1: Wake up by address mark.

PCE: Parity control enable

PS: Parity selection 0: Even parity; 1: Odd parity.

PEIE: PE interrupt enable (PE interrupt enable)

TXEIE: Transmit buffer empty interrupt enable (TXE interrupt enable)

TCIE: Transmission complete interrupt enable

RXNEIE: Receive buffer not empty interrupt enable (RXNE interrupt enable)

IDLEIE: IDLE interrupt enable 0: Disable interrupt; 1: Generate USART interrupt when IDLE in USART_SR is '1'.

TE: Transmitter enable

RE: Receiver enable

RWU: Receiver wakeup 0: The receiver is in normal working mode; 1: The receiver is in silent mode.

Note: 1. Before putting USART into silent mode (setting RWU bit), USART must have received a data byte first. Otherwise, it cannot be awakened by idle bus detection in silent mode.

2. When configured as address mark detection wake-up (WAKE bit = 1), the RWU bit cannot be modified by software when the RXNE bit is set.

SBK: Send break frame

The sending and receiving of data is realized in USART_DR, which is a double register, including TDR and RDR. When data is written to this register, the serial port will automatically send the data; when data is received, it is also stored in this register and can be read directly. Only the lower 9 bits of this register are valid (8:0), and the other bits are reserved.

The serial port status is read through the status register USART_SR, and each bit is described as follows:

TXE: Transmit data register empty

This bit is set by hardware when the data in the TDR register is transferred to the shift register by hardware. If TXEIE in the USART_CR1 register is 1, an interrupt is generated. A write operation to USART_DR clears this bit.

0: Data has not yet been transferred to the shift register;

1: Data has been transferred to the shift register.

TC: Transmission complete

This bit is set to '1' by hardware when a frame containing data is sent and TXE = 1. If TCIE in USART_CR1 is '1', an interrupt is generated. This bit is cleared by software sequence (read USART_SR first, then write USART_DR). The TC bit can also be cleared by writing '0'. This clearing procedure is only recommended in multi-buffered communication.

RXNE: Read data register not empty

When the data in the RDR shift register is transferred to the USART_DR register, this bit is set by hardware to indicate that the data has been received. If the RXNEIE bit in the USART_CR1 register is 1, an interrupt is generated. A read operation on the USART_DR can clear this bit. The RXNE bit can also be cleared by writing 0, which is only recommended in multi-buffer communication.

The code for directly operating registers is as follows: (For system.h, stm32f10x_it.h and other related codes, refer to the stm32 direct operation register development environment configuration)

User/main.c

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#endif

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