S3C6410 interrupt and external interrupt

In the interrupt processing of embedded software, in addition to interrupt initialization, the main work is to write ISR.
 
  In the CPU of embedded SOC, there are some device modules inside the CPU, and the interrupts they generate are called internal interrupts. Because the connection is relatively fixed, programming is relatively simple. In addition, the interrupts generated by the physically separated CPU chip are called external interrupts. External interrupts can be connected to different interrupt pins, so it is necessary to configure the interrupt IO in a more complex way.
 
  Is the polling mode useless? The advantage of polling is that polling is much more efficient than interrupts under heavy load. For example, in a classroom, many students keep asking questions. In this way, instead of being interrupted constantly, the teacher might as well get up and walk around the classroom, and randomly handle students' questions. Exception -------------------------------------------------------------------------- Exception, in computer architecture, exceptions or interrupts are a mechanism for handling emergencies in the system, and almost all processors provide this mechanism.
 
 
Exceptions are mainly a description from the perspective of passive acceptance by the processor, referring to exceptions caused by unexpected operations. Interrupts, on the other hand, carry the meaning of actively applying to the processor. However, these two situations have certain commonalities, both of which are a mechanism for requesting the processor to interrupt the normal program execution process and enter a specific program. From the structural point of view, the interrupt generated by the external device can be regarded as a special exception. In addition to interrupts, there are many fixed exceptions in ARM. Including the following seven: 1. Reset (Reset) When the RESET key is pressed, a reset exception will be generated. At this time, the program will jump to the reset exception handler for execution. When the CPU restarts, it will generally jump to this reset exception. 2. Undefined instruction When the ARM processor or coprocessor encounters an instruction that cannot be processed, an undefined instruction exception is generated. With this mechanism, the ARM or Thumb instruction set can be extended through software simulation. 3. Software interrupt (SWI) Hardware interrupts are interrupts generated by fixed hardware, while soft interrupts are interrupts generated by no specific hardware and are virtualized by the CPU. The exception is generated by the program executing the assembly SWI. The advantage of soft interrupts         can be used for programs in user mode to call privileged operation instructions. Linux system calls are implemented using this exception.         There are optimizations that utilize program structure. For example, in Linux In the driver, hardware interrupts cannot run for a long time. However, the long-term operation of many software depends on the call of interrupts. Sometimes, in order to resolve this conflict, the driver design will be two-level, using hardware interrupts for hardware access and simulating software interrupts for long-term operation. 4. Instruction prefetch abort If the address of the instruction to be prefetched does not exist, or the address does not allow the current instruction to access, the memory will send an abort signal to the processor, but when the prefetched instruction is executed, the instruction prefetch abort exception will be generated. For example, using ADS to download the program to the 0x8000 address on the development board, an Abort exception will be generated. 5. Data abort If the address of the processor data access data does not exist, or the address does not allow the current instruction to access, a data abort exception will be generated6 . IRQ When an external device generates an interrupt signal on the external interrupt pin, the IRQ interrupt is triggered. This is the most common method used by external devices. In S3C24X0, an integrated SOC, in addition to the ARM module, there are other internal integrated modules, such as USB, RTC, etc. These modules will also have corresponding interrupt lines connected to the core of ARM920T inside the CPU. However, these pins are invisible outside the CPU and can only be controlled by registers. Some GPIO pins act as external interrupt control lines, and external ICs can connect their own interrupt signal lines to the corresponding interrupt pins. When an external interrupt signal is generated, the CPU can know that an external interrupt has been sent. 7. FIQ fast interrupt, similar to IRQ, but with a faster response speed. And the conditions for setting FIQ are also stricter. For example, there can only be one FIQ in a trigger     . Interrupts (IRQ, FIQ, SWI) are a special case in the exception. When an external interrupt occurs, most CPUs will only generate one exception. In the exception handler, the software reads different interrupt registers for analysis and then calls the ISR. Here, the ISR is executed by software. S3C2440 has such a mechanism.    In S3C6410, a simplified interrupt processing flow can also be adopted. The CPU directly calls the interrupt ISR to process. In this way, the difficulty of writing interrupt processing software is greatly reduced. The addresses of vector   exception handling functions or interrupt handling functions are arranged in a continuous memory in the order of the interrupt number. From the perspective of C language, it can be regarded as a pointer array. The array is also called a vector. If you are familiar with the interrupt handling mechanism of S3C2440, you can find that S3C6410 greatly simplifies interrupt programming.    Compared with the detailed and rich explanation of interrupts in S3C2440, the datasheet of S3C6410 is obviously a rush work. There are only 15 pages about interrupts, and a large amount of content is still register tables.    Therefore, most of the following are reversed from the test program and Application Note of S3C6410. And re-write the program with ADS to verify. The main improvement of the interrupt of S3C6410 is   to add an interrupt vector controller, so that the interrupt processing mechanism that needs to be jumped by software in S3C2440 is completely jumped by hardware in S3C6410. You only need to store the ISR address in the continuous vector register space, instead of allocating space and managing it by yourself like S3C2440.   In other words, under S3C2440, the CPU triggers the IRQ/FIQ exception, and then searches the relevant interrupt register in the exception handling function to jump to the specified ISR, but all of this can be automatically handled by the VIC hardware of S3C6410. This greatly simplifies interrupt processing programming.  Another is to add a filtering circuit to the external interrupt, so that the places that originally required software deburring can be filtered by hardware, which greatly simplifies external interrupt processing. S3C6410 interrupt operation  --------------------------------------------------------------------   S3C6410 interrupt number

 




























































 





     





 


 











 
 

 

 
   
 

 

 

 






 




 

The 64 interrupts are divided into two groups, VIC0 and VIC1, according to the hardware grouping. Each group is handled by a corresponding register.
     Interrupt numbers 0-31 are in the VIC0 group ,
     and interrupt numbers 32-63 are in the VIC1 group .
 
The S3C6410 interrupt operation is very simple.
 
Turn on the interrupt VICxINTENABLE. 
  x is 0, 1. Interrupts 0-31 use VIC0INTENABLE, and interrupts 32-63 use VIC1INTENABLE. The following registers are the same and will not be repeated.
 
The corresponding bit is 1, indicating that the interrupt is available. If interrupt number 0 is valid, the 0th bit of VIC0INTENABLE is 1.


 

Turn off an interrupt
    . Set the corresponding bit of VICxINTENCLEAR to 1 to turn off the interrupt.


 

Set the interrupt type
  to set whether an interrupt is IRQ or FIQ. Note that only one interrupt can be FIQ. Setting the corresponding bit to 1 means setting it to FIQ mode.

Set the vector address (ISR address) of S3C6410.
   Note that S3C6410 itself has two register arrays with 32 consecutive addresses. The first addresses are 0x71200100 and 0x71300100 respectively. You can operate them like pointer arrays. The subscript of the array is the interrupt number. Each interrupt source corresponds to its own interrupt address bit. There are 64 interrupt sources in total, so there are two 32*32 arrays.
   This setting greatly simplifies the vector organization of ISR for developers.


 

Setting the interrupt priority
   also uses 32*2 registers to form two priority arrays. Each register corresponds to a priority level, and the value range is between 0-15.

 

After the interrupt is run,
   this is indicated because in order to use VIC, a lot of S3C2440 registers such as SRCPND, INTPND, INTOFFSET, SUBSRCPND are now omitted. VICxADDRESS is used to indicate the current ISR address directly.  
 


 
  Note that the VICxADDRESS register is called System BUS in S3C6410. This method is not recommended because it is equivalent to using software to jump to ISR in S3C2440.
   This is the reference process given by Samsung.

A simpler calling method is the VIC port mode, which is the mode I strongly recommend. When the system generates an interrupt, the VIC will directly execute the corresponding ISR. This not only makes programming simpler, but also more efficient, because it does not require access to VICxADDRESS and time to execute on the System BUS.
To use this mode, you only need to add specific code at startup.

 

External interrupt programming

Except for INT_EINT0-INT_EINT4, all interrupts are triggered by the internal module of S3C6410. The so-called internal interrupts


  INT_EINT0-INT_EINT4 are external interrupts, which are triggered by peripherals outside the CPU. Which interrupt is triggered depends on which GPIO interrupt pin the peripheral is connected to. 
   Network controllers and buttons on the development board are all hung on certain GPIO pins. They all use typical external interrupts.
 
External interrupt pins
S3C6410 is divided into 9 groups of GPIO pins to act as external interrupt pins
  Group 0, a total of 28 pins. GPN0-GPN15 (16 pins), GPL8-GPL14 (7 pins), GPM0-GPM4 (5 pins)
  Group 1, GPA0-GPA7, 8 interrupt pins, GPB0-GPB7, 8 interrupt pins
  Group 2, GPC0-GPC0, a total of 8 interrupt pins…
     …
  Group 8, GPP0-GPP14, 15 interrupt pins in total
  Group 9, GPQ0-GPQ8, 9 interrupt pins in total
 
External interrupt number
 
The devices from pin 0 to pin 3 of group 0 will trigger INT_EINT0=0 interrupt
Pins 4-11 of group 0 will trigger INT_EINT1=1 interrupt
Pins 12-19 of group 0 will trigger INT_EINT2=32 interrupt
Pins 20-27 of group 0 will trigger INT_EINT3=33 interrupt
All devices from group 1 to group 9 will only trigger INT_EINT4=53 interrupt
 
We can see that multiple interrupt pins in each group share one interrupt number. Group 0 is more commonly used, occupying 3 interrupt numbers, and each pin has its own sub-interrupt. Groups 1-9 share one interrupt number, and each group has one sub-interrupt source.


 

In ISR, how to determine which interrupt pin generated the interrupt?
 
Multiple devices on different IO pins generate the same interrupt, how does the software know which pin it is?
Determine by External Interrupt Pending Register

Group 0 is determined by EINT0PEND. The pin correspondence can be referred to the figure above, which is not very regular.

Groups 1 and 2 are determined by EINT12PEND

And so on, EINT34PEND, EINT56PEND, and so on to EINT9PEND to indicate

External interrupt signal type
 
  Here you set what kind of signal the interrupt generates to be captured. There are mainly five types, low level, high level, rising edge, falling edge or both.
Group 0 uses EINT0CON0/EINT0CON1 two registers to set.
 


 
Groups 1 and 2 use EINT12CON,
groups 3 and 4 use EINT34CON,
and so on.

 

Temporarily disable external interrupts
EINTxMask is to temporarily disable interrupts.
1 means to disable an interrupt, 0 means to enable it. Generally, interrupts are enabled only when they are needed. 


EINT0MASK is used for group 0,


EINT12MASK is for groups 1 and 2,


 and so on...
 

Define the hardware filter type.


  For some external interrupt signals with irregular waveforms, the filter circuit can make them regular, which will simplify the software writing.


 S3C6410 has two filter circuits, one is delay filter (such as button interrupt can use this type), and the other is digital sampling filter. The second filter circuit also needs to set the sampling width.


  The filter of group 0 is configured with EINT0FLTCON0, EINT0FLTCON1, EINT0FLTCON2, EINT0FLTCON3.


 FLTEN indicates whether to turn on the filter function, FLTSEL is to set the filter mode, and EINTn indicates the width of the digital filter sampling.
 

The first and second groups of filters use EINT12FLTCON.
The third and fourth groups of filters use EINT34FLTCON.


The ninth group of filters uses EINT9FLTCON.
 

External interrupt programming
 
  In addition to all interrupt programming processes,
  external interrupts generally configure the corresponding GPxCON to configure it as an interrupt pin.
   You also need to configure the filtering method and interrupt signal method.
 


  You also need to open the external interrupt mask
 
  in the ISR. In the end, in addition to clearing VICxADDRESS to 0, you also need to clear the corresponding bit of VICxSOFTINTCLEAR.
 
Software interrupt programming
-------------------------------------------------------------
 There are 64 soft interrupts in S3C6410 (corresponding to hardware interrupts), and this description is very vague. Can the same hardware interrupt be triggered by software or is there a completely corresponding software interrupt? This requires software verification.
 
  All processes of soft interrupts except hardware interrupts must add the following two items.
  Use VICxSOFTINT to trigger the soft interrupt and
  use VICxSOFTINTCLEAR to clear the status when the ISR exits

Soft interrupt programming process