1 SPCE061A board and PTR8000 hardware connection
Figure 1 shows the hardware connection diagram of SPCE061A microcontroller and PTR8000.
2 Working principle of SPI bus of PTRS000 communication module
The PTR8000 communication module acts as a slave device, and its SPI interface uses four I/O lines: the serial clock line SCK, the output data line MISO, the input data line MOSI, and the high-level effective slave select line CSN. The PTR8000 SPI bus interface read command timing is shown in Figure 2. The write command is shown in Figure 3.
3. Implementation method of software simulation SPI interface
For the SPCE061A microcontroller that does not have an SPI serial bus interface, software can be used to simulate the operation of SPI. In Figure 1, IOB1 simulates the data output terminal SDO of the SPI master device, IOB0 simulates the clock output terminal SCK of the SPI, IOA4 simulates the slave selection terminal CSN of the SPI, and IOB9 simulates the data input terminal SDI of the SPI.
After power-on reset, the initial state of IOB0 (SCK) is first set to 0 (idle state).
Read operation: SPCE061A first sends 1 start bit (1), 2 operation codes (10), and 6 data addresses to be read through IOB1 port, then reads 1 empty bit through IOB9 port, and then reads 16 bits of data (high bit first).
Write operation: SPCE061A first sends 1 start bit (1), 2 operation codes (01), and 6 data addresses to be written through the IOB1 port, and then sends the 16-bit data to be written (high bit first) through the IOB1 port. A write enable command must be sent before the write operation, and a write disable command must be sent after the write operation.
Write enable operation (WEN): A write operation first sends a 1-bit start bit (1), a 2-bit operation code (00), and 6-bit data (11XXXX).
Write disable operation (WDS): The write operation first sends a start bit (1), a 2-bit operation code (00), and 6 bits of data (00XXXX).
The following introduces the subroutine for simulating SPI using SPCE061A.
For different serial interface peripheral chips, their clock timing is different. The above subroutines are for devices that input (receive) data on the rising edge of SCK and output (send) data on the falling edge. These subroutines are also applicable to various other serial peripheral interface chips that input on the rising edge and output on the falling edge of the serial clock. Just change the output level sequence of IOB0 (SCK) in the program and make corresponding adjustments.
4 Conclusion
This article introduces the method of realizing data transmission between non-SPI interface microcontroller and SPI interface memory by software simulation of SPI bus interface, and gives a subroutine written by SPCE061A to simulate SPI serial bus reading PTR8000. This method is also applicable to other microcontrollers, ARM, microcomputers, etc.
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Recommended ReadingLatest update time:2024-11-16 22:38
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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