mini2440 timer study notes

    S3C2440 has 5 16-bit timers. Timers 0, 1, 2 and 3 have PWM functions (so these 4 timers are also called PWM timers), all have an output pin, and timer 4 is an internal timer without an external output pin. The
   clock source of the timer is PCLK, which is then divided by the internal two-stage divider to obtain the frequency required for the timer to work. Among them, timers 0 and 1 share an 8-bit first-stage prescaler prescaler 0, and timers 2, 3, and 4 share another 8-bit first-stage prescaler prescaler 1; each timer has a corresponding second-stage divider clock divider as shown in the figure below.

Although there are many timers, the working principles are the same. You only need to understand the working principle of one timer. For a certain timer, its internal structure schematic diagram is shown in Figure 2. The cache registers TCMPBn and TCNTBn are used to cache the comparison value and initial value of timer n; TCON is used to control the start and end of the timer; the current count value of the timer is obtained by reading the register TCNTOn.
 




                                    Overview of the working principle of the timer:
 ① First, load the comparison value and initial value of the timer into registers TCMPBn and TCMPBn
 ② Then, set the timer control register TCON and start the timer. At this time, the values ​​in TCMPBn and TCNTBn will be loaded into registers TCMPn and TCNTn.
 ③ At this time, the timer will count down by 1, that is, TCNTn will count down by 1. When TCMPn=TCNTn, the output of the TOUTn pin is opposite.
 
                                         Timer initialization①
 Timer clock frequency (for example, if the timer clock frequency is 50, then the 1-second count register will be subtracted by 50; if it is 100, then the 1-second count register will be subtracted by 100);
 ② Set the timer count value (for example, if the initial count value is 100 and the timer clock frequency is 50, an interrupt will occur after two seconds, such as the pin outputting the opposite level);
 ③ Set the interrupt processing function①
 
 
 
   Clock frequency initialization: Timer clock frequency = PCLK/(prescaler+1)/(divider value)
Among them: prescaler value = 0~255 (its value is set by the TCFG0 register, as shown in the figure below)
      divider value = 2,4,8,16 (its value is set by the TCFG1 register, as shown in the figure below)
 

TCFG0	Bit	describe	Initial Value
reserve	[31:24]		0x00
Dead zone length	[23:16]	These 8 bits determine the length of the dead zone. The unit time of the dead zone length is equal to the unit time of timer 0.	0x00
Prescaler 1	[15:8]	These 8 bits determine the pre-scaler value of timer 2, 3, and 4.	0x00
Prescaler 0	[7:0]	These 8 bits determine the pre-scaler value of timer 0 and 1.	0x00

 

 
 
     ② Count value initialization: These two registers store the set count comparison values, which can be directly assigned. The following takes timer 0 as an example:

TCMPB0	Bit	describe	Initial Value
Timer 0 computer buffer register	[15:0]	Set compare buffer value for Timer0	0x00000000

 
 

TCNTB0	Bit	describe	Initial Value
Timer 0 count buffer register	[15:0]	Set count buffer value for Timer 0	0x00000000

 
    ③ Set the interrupt processing function and write it yourself.
 
Example 1: Combined with the above explanation, we can know that the input clock of timer 0 is obtained by dividing the PCLK. The figure below shows its generation process. -------------------------------------Dividing line--------------------------------------------------- Analysis: In the previous question, two timer configuration registers TCFG1 and TCFG0 appear. Among them, the TCFG0 configuration register controls the division coefficient of the first-level divider prescaler, and the TCFG1 configuration register controls the multi-way selection switch to select the division coefficient of the second-level divider divider. The details are shown in the following figure: -----------------------------------------Dividing line----------------------------------------------------- -----------------------------------------Dividing line--------------------------------------------------- Example 2: PCLK is 50MHz, please set an appropriate division coefficient to make the input clock of timer 0 62.5kHz. Answer: Knowing that PCLK is 50MHz, 50MHz/62.5kHz=800, that is, PCLK needs to be divided by 800. Therefore, the frequency division coefficient of the first-stage frequency divider is 100, and the frequency division coefficient of the second stage is 8 to meet the requirements. Finally, you only need to write the frequency division coefficient to the corresponding bit in the timer control register. The code is as follows: 1  rTCFG0&=~(0xFF); clear the lower 8 bits of TCFG0 2  rTCFG0|=99; because the frequency division coefficient = prescaler+1, that is, prescaler+1=100, so prescaler value=99 3  rTCFG1&=~(0xF); clear the lower 4 bits of TCFG1