How to Reduce Ripple in a PWM DAC in a Microprocessor

Jacktang

How to Reduce Ripple in a PWM DAC in a Microprocessor [Copy link]

There are two common methods for reducing ripple in PWM DACs: one is to lower the cutoff frequency of the low-pass filter, and the other is to increase the frequency of the PWM signal. However, the former method will increase the rise time, and the latter method will result in reduced resolution. This design idea discusses how to reduce the ripple of a PWM DAC without using the above two methods.
　　Most of us are familiar with PWM DACs (digital-to-analog converters). They are easy to implement, inexpensive, and well suited for some low-performance applications.
　　They are implemented by filtering out the high-frequency components of the PWM signal, leaving only the low-frequency or DC components that are proportional to the duty cycle. However, the low-pass filter cannot completely filter out the PWM frequency, so there is usually a certain degree of ripple in the low-frequency/DC signal.
　　There are two common methods for reducing ripple in PWM DACs. One is to lower the cutoff frequency of the low-pass filter, and the other is to increase the frequency of the PWM signal. However, it is inevitable that a lower cutoff frequency will increase the rise time, and if it is achieved by reducing the counter size at a given clock frequency, then a faster PWM frequency will reduce the resolution.
　　The design idea discussed below is very interesting and highlights another method for reducing ripple in PWM DACs.
　　In fact, we can use two PWM signals with a phase difference of 180° to reduce the above ripple. Intuitively, when two sine waves of the same frequency have a phase difference of 180°, they will cancel each other, so we can also cancel each other's harmonic components by using two PWM signals with a phase difference of 180°, right? It is true, but not all harmonic components of the PWM signal can be cancelled, some components can be cancelled, and some cannot be cancelled. This is related to the Fourier series, which is relatively complicated, so I will not list a lot of mathematical formulas here to explain it.
　　How is the 180° phase difference between the two PWM signals achieved? I used TI's MSP320FR5969 LaunchPad, and this method is very common. In order to achieve phase shifting, two timers are required. One of the timers must contain two compare-capture-PWM (CCP) modules, and the other only needs one CCP module.
　　In the timer containing two CCP modules, one CCP module can be used to set the PWM frequency and duty cycle of the timer, and the other CCP module generates an interrupt to start another timer, and the delay between the two is equal to half of the PWM period. The CCP module in the other timer is used to set the same PWM frequency and duty cycle. You also have to "tune" this delay, because the software will add extra time between the PWM signals. For example, in line 102 of my code, I changed the compare register value from (timer_period+1)/2 to (timer_period+1)/2-27.
　　I did some research to see if other microcontrollers have the same hardware and capabilities to implement the method I used: many Atmel microcontrollers have more than 1 timer, and each controller usually has two CCPs (such as the ATmega 328), so it should be possible to implement this method. Another common example is the STM32F051R8 (this is the microcontroller used in some popular ST boards), which has 11 timers, many of which have more than 1 CCP. TI ARM-based microcontrollers usually have separate PWM and timer modules (such as the TM4C123GH6PM), so it should be easier to implement phase shifting. Using one of the timers, the two PWM modules can be turned on with a delay of half the PWM period.

　　Figure 1: Single and dual PWM circuits.
　　At the Vout end of the phase-shift DAC, the two PWM signals are summed together, resulting in some harmonic components canceling each other, ultimately achieving the effect of reducing ripple.
　　Let's look at the situation when using three different resistor values. Each PWM signal has a duty cycle of 25% and a frequency of 100kHz.

　　Figure 2: The top waveform is a traditional PWM, and the bottom waveform is a dual phase-shifted PWM. From left to right, the voltage of each grid decreases by 100mV, 50mV, and 4mV.
　　From the results in the figure, we can see that: first, the peak-to-peak ripple is reduced; second, the ripple fundamental frequency of the traditional PWM DAC is equal to the frequency of the PWM signal (100kHz). The ripple fundamental frequency of the phase-shifted PWM DAC is equal to the second harmonic of the PWM signal (200kHz), which means that we have successfully removed the first harmonic of the PWM signal with the phase-shifted DAC.
　　One advantage of this method is that the ripple can be reduced without increasing the rise time (or the same ripple only needs half the rise time).
　　Another potential advantage is that setting the two PWMs one count apart can obtain intermediate values, thereby doubling the effective resolution of the DAC. Although this will cause a small amount of asymmetry and increase ripple, the effect is small and can be ignored.