ARM architecture detailed explanation of ARM registers

　　What we need to pay special attention to here is the difference between ARM's own registers and some of its peripheral registers.

　　ARM itself is a unified architecture, which means that the 37 registers will appear in any company's chip. However, each company will expand ARM peripherals, so there are many peripheral registers, which must be distinguished from these 37 registers!!!

　　1. Backup registers (R8-R14)

　　For R8-R12, except in fast interrupt mode, each mode corresponds to the same physical register, so it is not necessary to protect and restore the interrupt scene in FIQ mode.

　　For R13-R14, each register corresponds to 6 different physical registers, one of which is shared by user mode and system mode.

　　Register R13 is often used as the stack pointer SP. Except for user and system modes, the names of other modes when used are composed of R13_.

　　Register R14 is also called the link register (LR). Except for user and system modes, the names of other modes when used are composed of R14_.

　　R14 has the following two special uses:

　　A. Each processor mode stores the return address of the current subroutine in its own physical R14. When a subroutine is called through a BL or BLX instruction, R14 is set to the return address of the subroutine.

　　B. When an exception interrupt occurs, R14 in the exception mode is set to save the return address based on the PC of the mode. For some exception modes, the value of R14 may have a constant offset from the address to be returned, and the offset may be different for different modes (detailed introduction in ARM exception handling).

　　2. Ungrouped registers (R0-R7)

　　No grouping means that the same physical register is used in all processor modes. When the processor mode is switched due to an abnormal interrupt, different processor modes use a physical register with the same name, which means the same register is used. This may cause the data in the register to be destroyed, so it must be protected when switching modes.

　　3. Program counter R15

　　For users, try to avoid using STR/STM instructions to save the value of R15. When an address value is successfully written to R15, the program will jump to the address for execution.

　　In ARM state, instructions are always word-aligned, so the PC[1:0] bits of the PC are always zero. When you want to write an address to the PC, be sure to set PC[1:0] to zero.

　　ARM uses a three-stage pipeline structure, so PC points to the next two instructions of the currently executed instruction, and PC-8 is the address of the current instruction.

　　4. Program Status Register

　　The CPSR (Current Program Status Register) can be accessed in any processor mode. At the same time, in addition to user and system modes, each processor mode has a dedicated physical status register called SPSR (Backup Program Status Register). When a specific exception interrupt occurs, this register is used to store the contents of the current program status register. When accessing the SPSR in user mode and system mode, unpredictable results will occur.

　　The format of CPSR and SPSR is the same, as follows:

　　0:M0

　　1:M1

　　2:M2

　　3:M3

　　4:M4

　　5: T (=1 Thumb execution)

　　6: F (=1 is prohibited)

　　7: I (=1 is prohibited)

　　Note: Not all combinations of M0~M4 define valid processing modes. If incorrect settings are made, unpredictable errors may occur.

　　27:Q In the ARM V5 E series processors, bit[27] of CPSR is called the q flag, which is mainly used to indicate whether the enhanced dsp instruction has overflowed. Similarly, bit[27] of spsr is also called the q flag, which is used to save and restore the Q flag in CPSR when an abnormal interrupt occurs.

　　In versions prior to ARM V5 and non-E series processors of ARM V5, the Q flag is not defined

　　28: V For addition and subtraction instructions, when the operands and the results are signed numbers represented by binary's complement, V=1 indicates that the sign is overflow; usually other instructions do not affect the V bit.

　　For other instructions, the V system usually does not change.

　　29:C The following discusses the setting method of C in four cases:

　　In addition instructions (including comparison instructions CMN), when the result produces a carry, C=1, indicating that an overflow occurs in the unsigned operation; in other cases, C=0.

　　In subtraction instructions (including subtraction instruction CMP), when a borrow occurs during the operation, C=0, indicating that the unsigned operand has underflowed; in other cases, C=1.

　　For non-addition and subtraction instructions that include shift operations, C contains the value of the last bit shifted out.

　　For other non-addition and subtraction instructions, the value of the C bit is usually not affected.

　　30:Z z="1 means the result of the operation is zero"; z=0 means the result of the operation is not zero. For the CMP instruction, Z=1 means the two numbers being compared are equal.

　　31:N When two signed integers are operated on, n=1 means the result of the operation is a negative number, and n=0 means the result is a positive number or zero.

　　MRS: Transfer instruction from status register to general register.

　　MSR: general register to status register transfer instruction