1 S3C2440 interrupt register

         Interrupts are divided into two categories: external interrupts and internal interrupts.

1.1 External Interrupt Register

         24 external interrupts occupy GPF0-GPF7 (EINT0-EINT7), GPG0-GPG15 (EINT8-EINT23). If you use these pins as interrupt inputs, you must configure the pins as interrupts and do not pull them up. For details, please refer to the datesheet data manual.
Registers:
             EXTINT0-EXTINT2: Set the trigger mode of EINT0-EINT7, EINT8-EINT15, EINT16-EINT23 respectively (high level trigger, low level trigger, falling edge trigger, rising edge trigger).
             EINTFLT0-EINTFLT3: Control the filter clock and filter width.
             EINTPEND: This is the interrupt pending register. When clearing, write 1. There are several more to write 1 to clear. When an external interrupt (EINT4-EINT23) occurs, the corresponding bit will be set to 1. Why there is no EINT0-EINT3, because they are controlled by the last 4 bits of the SRCPND register.
           EINTMASK: This is simple, it is used to mask interrupts, that is, when the bit is 1, the interrupt is invalid.

1.2 Internal Interrupt Register

           There are 8 internal interrupt registers.

Register:
           SUBSRCPND: When an interrupt occurs, the corresponding bit will be set to 1, indicating that an interrupt has occurred.
           INTSUBMSK: Same as the previous one, interrupt mask register.
           SRCPND: When an interrupt occurs, the corresponding bit will be set to 1, indicating that one or a class of interrupts has occurred.
           INTMSK: Used to mask the interrupt identified by the SRCPND register. But only IRQ interrupts can be masked, not FIQ interrupts.
           INTMOD: When a bit in INTMOD is set to 1, the corresponding interrupt is set to FIQ, and the CPU will enter the fast interrupt mode.
           PRIORITY: Used to set the priority of the IRQ interrupt. For specific usage, please refer to the chip manual.
           INTPND: After the interrupt priority arbiter selects the interrupt with the highest priority, the corresponding bit of this interrupt in the INTPND register is set to 1, and then the CPU enters the interrupt mode to handle it. At the same time, only one bit of this register is set to 1.
           INTOFFSET: Used to indicate which bit in the INTPND register is set to 1, that is, to record the value of bit x in INTPND where bit [x] is 1. Automatically cleared when INTPND and SRCPND are cleared.

1.3 Relationship between registers:

Figure 1 Relationship between interrupt registers

2 Interruption process

2.1 Internal interrupt process

a If it is an internal interrupt without sub-interrupt: after it occurs, the corresponding position of SRCPND is set to 1. If it is not masked by INTMSK, it waits for further processing.
b If it is an internal interrupt with sub-interrupt: after it occurs, the corresponding position of SUBSRCPND is set to 1. If it is not masked by INTSUBMSK, the corresponding position of SRCPND is set to 1, waiting for further processing. Several SUBSRCPNDs may correspond to the same SRCPND. The corresponding table is as follows:
 

2.2 External interrupt process

a If it is an external interrupt: After EINT0-EINT3 occurs, the corresponding position of SRCPND is set to 1. If it is not masked by INTMSK, it waits for further processing. After EINT4-EINT23 occurs, the corresponding position of EINTPEND is set to 1. If it is not masked by EINTMASK, the corresponding bit EINT4-7 or EINT8-23 of SRCPND is set to 1. If it is not masked by INTMSK, it waits for further processing. Several EINTPENDs correspond to the same SRCPND. The corresponding table is as follows:
 

           All three interrupts are waiting for further processing. Next, look down from SRCPND to INTMSK. If the interrupt is blocked, there is no need to say anything (note: fast interrupts can also be blocked). If it is not blocked, it will go further to INTMOD. If it is a fast interrupt, it will come out directly and enter FIQ (that is, the CPU enters fast interrupt mode for processing). If it is a normal interrupt, then SRCPND can be set to 1 multiple times (FIQ can only have one), then PRIORITY will be used to select a high priority, and then the corresponding position of INTPND will be set to 1 according to the selected interrupt (note: only one can be selected), enter IRQ, and let the CPU process it.

2.3 Enabling interrupts

a. If it is an internal interrupt without sub-interrupt, just set INTMSK to make it unmask the interrupt.
b. If it is an internal interrupt with sub-interrupt, set INTSUBMSK and INTMSK to make them unmask the interrupt.
c. If it is an external interrupt, for EINT8-23, you need to set EINTMASK and INTMSK. For EINT0-EINT3, you only need to set INTMSK.

2.4 Clearing Interrupts

a. If it is an internal interrupt without sub-interrupt, just clear SRCPND. Note that the clearing position needs to be 1.
b. If it is an internal interrupt with sub-interrupt, clear SRCPND and SUBSRCPND. Note that SUBSRCPND should be cleared first, then SRCPND. Because if you clear SRCPND first, then in the process of clearing SUBSRCPND, SRCPND will think that another interrupt has occurred and will be set to 1 again. In other words, an interrupt will be responded to twice. So the source must be cut off first.
c. If it is an external interrupt, for EINT8-23, you need to clear EINTPEND and SRCPND (also pay attention to the order). For EINT0-EINT3, you only need to clear SRCPND.