ARM Nand Flash Control-EEWORLD

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Summary of this chapter

I personally think that the content of this chapter is too complicated. You only need to remember that if the 4096 program in nand wants to be copied and executed, just write this code in. The red part is the real code, which can be copied and used directly. I don’t need to understand the rest. After listening for an hour, the teacher’s lecture is quite confusing. No one can remember so many things. . .

【head.S init.c main.c nand.c Makefile】

Detailed explanation of the code: Here, a part of the code is stored after NAND Flash address 4096. When the program is started, it is read out and executed through the NAND Flash controller.

Note: All previous codes are less than 4096, and they are automatically copied into "Steppingstone" after the development board is started;

The current code is after 4096, and we need to control NAND Flash to read and execute them.

【nand.lds】

SECTIONS {

firtst 0x00000000 : { head.o init.o nand.o}

second 0x30000000 : AT(4096) { main.o }

}

Here is how I understand it. head.o init.o nand.o are all placed at the address of Nand flash 0, 0x0000 0000 is its link address, that is, it is placed at 0x0000 0000 to run; main.o is stored at the address of Nand flash 4096, 0x3000 0000 is its link address, that is, it is placed at 0x3000 0000 to run

(This may be the difference between the link address and the load address I saw a while ago)

When the development board starts, the first 4k of code is loaded into SRAM, so we need to complete the initialization and jump in SRAM

【head.s】

SECTIONS {

firtst 0x00000000 : { head.o init.o nand.o}

second 0x30000000 : AT(4096) { main.o }

} @************************************************ ****************************

@File:head.s

@ Function: Set up SDRAM, copy the program to SDRAM, and then jump to SDRAM to continue execution

@****************************************************** *****************************

.text

.global _start

_start:

@Functions disable_watch_dog, memsetup, init_nand, nand_read_ll are defined in init.c

ldr sp, =4096 @Set up the stack

bl disable_watch_dog @offWATCH DOG

bl memsetup @ Initialize SDRAM

bl nand_init @Initialize NAND Flash

@Copy the 1024-byte code starting at address 4096 in NAND Flash (compiled from main.c) to SDRAM

The @nand_read_ll function requires 3 parameters:

ldr r0, =0x30000000 @1. Target address = 0x30000000, which is the starting address of SDRAM

mov r1, #4096 @2. Source address = 4096. When linking, the code in main.c is stored at the beginning of NAND Flash address 4096.

mov r2, #2048 @3. Copy length = 2048 (bytes), which is enough for main.c of this experiment

bl nand_read @Call C function nand_read

ldr sp, =0x34000000 @Set up the stack

ldr lr, =halt_loop @Set the return address

ldr pc, =main @b instruction and bl instruction can only jump forward and backward within the range of 32M, so here we use the method of assigning value to pc to jump

halt_loop:

b halt_loop

*For this string of codes, many of them are knowledge learned before. Here we only focus on the red code for configuring Nand.

bl nand_init

*Destination address, source address, destination length

ldr r0, =0x30000000 @1. Target address = 0x30000000, which is the starting address of SDRAM

mov r1, #4096 @2. Source address = 4096. When linking, the code in main.c is stored at the beginning of NAND Flash address 4096.

mov r2, #2048 @3. Copy length = 2048 (bytes), which is enough for main.c of this experiment

bl nand_read @Call C function nand_read

Here we can jump to nand_read and take a look

void nand_read(unsigned char *buf, unsigned long start_addr, int size)

{

int i, j;

#ifdef LARGER_NAND_PAGE

if ((start_addr & NAND_BLOCK_MASK_LP) || (size & NAND_BLOCK_MASK_LP)) {

return ;

}

#else

if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {

return ;

}

#endif

nand_select_chip();

for(i=start_addr; i < (start_addr + size);) {

write_cmd(0);

write_addr(i);

#ifdef LARGER_NAND_PAGE

write_cmd(0x30);

#endif

wait_idle();

#ifdef LARGER_NAND_PAGE

for(j=0; j < NAND_SECTOR_SIZE_LP; j++, i++) {

#else

for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {

#endif

*buf = read_data();

buf++;

}

【nand.c】

#define LARGER_NAND_PAGE

#define GSTATUS1 (*(volatile unsigned int *)0x560000B0)

#define BUSY 1

#define NAND_SECTOR_SIZE 512

#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)

#define NAND_SECTOR_SIZE_LP 2048

#define NAND_BLOCK_MASK_LP (NAND_SECTOR_SIZE_LP - 1)

typedef unsigned int S3C24X0_REG32;

typedef struct {

S3C24X0_REG32 NFCONF;

S3C24X0_REG32 NFCMD;

S3C24X0_REG32 NFADDR;

S3C24X0_REG32 NFDATA;

S3C24X0_REG32 NFSTAT;

S3C24X0_REG32 NFECC;

} S3C2410_NAND;

typedef struct {

S3C24X0_REG32 NFCONF;

S3C24X0_REG32 NFCONT;

S3C24X0_REG32 NFCMD;

S3C24X0_REG32 NFADDR;

S3C24X0_REG32 NFDATA;

S3C24X0_REG32 NFMECCD0;

S3C24X0_REG32 NFMECCD1;

S3C24X0_REG32 NFSECCD;

S3C24X0_REG32 NFSTAT;

S3C24X0_REG32 NFESTAT0;

S3C24X0_REG32 NFESTAT1;

S3C24X0_REG32 NFMECC0;

S3C24X0_REG32 NFMECC1;

S3C24X0_REG32 NFSECC;

S3C24X0_REG32 NFSBLK;

S3C24X0_REG32 NFEBLK;

} S3C2440_NAND;

typedef struct {

void (*nand_reset)(void);

void (*wait_idle)(void);

void (*nand_select_chip)(void);

void (*nand_deselect_chip)(void);

void (*write_cmd)(int cmd);

void (*write_addr)(unsigned int addr);

unsigned char (*read_data)(void);

}t_nand_chip;

static S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;

static S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;

static t_nand_chip nand_chip;

void nand_init(void);

void nand_read(unsigned char *buf, unsigned long start_addr, int size);

static void nand_reset(void);

static void wait_idle(void);

static void nand_select_chip(void);

static void nand_deselect_chip(void);

static void write_cmd(int cmd);

static void write_addr(unsigned int addr);

static unsigned char read_data(void);

static void s3c2410_nand_reset(void);

static void s3c2410_wait_idle(void);

static void s3c2410_nand_select_chip(void);

static void s3c2410_nand_deselect_chip(void);

static void s3c2410_write_cmd(int cmd);

static void s3c2410_write_addr(unsigned int addr);

static unsigned char s3c2410_read_data();

static void s3c2440_nand_reset(void);

static void s3c2440_wait_idle(void);

static void s3c2440_nand_select_chip(void);

static void s3c2440_nand_deselect_chip(void);

static void s3c2440_write_cmd(int cmd);

static void s3c2440_write_addr(unsigned int addr);

static unsigned char s3c2440_read_data(void);

static void s3c2410_nand_reset(void)

{

s3c2410_nand_select_chip();

s3c2410_write_cmd(0xff); // reset command

s3c2410_wait_idle();

s3c2410_nand_deselect_chip();

}

static void s3c2410_wait_idle(void)

{

int i;

volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFSTAT;

while(!(*p & BUSY))

for(i=0; i<10; i++);

}

static void s3c2410_nand_select_chip(void)

{

int i;

s3c2410nand->NFCONF &= ~(1<<11);

for(i=0; i<10; i++);

}

static void s3c2410_nand_deselect_chip(void)

{

s3c2410nand->NFCONF |= (1<<11);

}

static void s3c2410_write_cmd(int cmd)

{

volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFCMD;

*p = cmd;

}

static void s3c2410_write_addr(unsigned int addr)

{

int i;

volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFADDR;

*p = addr & 0xff;

for(i=0; i<10; i++);

*p = (addr >> 9) & 0xff;

for(i=0; i<10; i++);

*p = (addr >> 17) & 0xff;

for(i=0; i<10; i++);

*p = (addr >> 25) & 0xff;

for(i=0; i<10; i++);

}

static unsigned char s3c2410_read_data(void)

{

volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFDATA;

return *p;

}

static void s3c2440_nand_reset(void)

{

s3c2440_nand_select_chip();

s3c2440_write_cmd(0xff); // reset command

s3c2440_wait_idle();

s3c2440_nand_deselect_chip();

}

static void s3c2440_wait_idle(void)

{

int i;

volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFSTAT;

while(!(*p & BUSY))

for(i=0; i<10; i++);

}

static void s3c2440_nand_select_chip(void)

{

int i;

s3c2440nand->NFCONT &= ~(1<<1);

for(i=0; i<10; i++);

}

static void s3c2440_nand_deselect_chip(void)

{

s3c2440nand->NFCONT |= (1<<1);

}

static void s3c2440_write_cmd(int cmd)

{

volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFCMD;

*p = cmd;

}

static void s3c2440_write_addr(unsigned int addr)

{

int i;

volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFADDR;

*p = addr & 0xff;

for(i=0; i<10; i++);

*p = (addr >> 9) & 0xff;

for(i=0; i<10; i++);

*p = (addr >> 17) & 0xff;

for(i=0; i<10; i++);

*p = (addr >> 25) & 0xff;

for(i=0; i<10; i++);

}

[page]

static void s3c2440_write_addr_lp(unsigned int addr)

{

int i;

volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFADDR;

int col, page;

col = addr & NAND_BLOCK_MASK_LP;

page = addr/NAND_SECTOR_SIZE_LP;

*p = col & 0xff;

for(i=0; i<10; i++);

*p = (col >> 8) & 0x0f;

for(i=0; i<10; i++);

*p = page & 0xff;

for(i=0; i<10; i++);

*p = (page >> 8) & 0xff;

for(i=0; i<10; i++);

*p = (page >> 16) & 0x03;

for(i=0; i<10; i++);

}

static unsigned char s3c2440_read_data(void)

{

volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFDATA;

return *p;

}

static void nand_reset(void)

{

nand_chip.nand_reset();

}

static void wait_idle(void)

{

nand_chip.wait_idle();

}

static void nand_select_chip(void)

{

int i;

nand_chip.nand_select_chip();

for(i=0; i<10; i++);

}

static void nand_deselect_chip(void)

{

nand_chip.nand_deselect_chip();

}

static void write_cmd(int cmd)

{

nand_chip.write_cmd(cmd);

}

static void write_addr(unsigned int addr)

{

nand_chip.write_addr(addr);

}

static unsigned char read_data(void)

{

return nand_chip.read_data();

}

void nand_init(void)

{

#define TACLS 0

#define TWRPH0 3

#define TWRPH1 0

if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))

{

nand_chip.nand_reset = s3c2410_nand_reset;

nand_chip.wait_idle = s3c2410_wait_idle;

nand_chip.nand_select_chip = s3c2410_nand_select_chip;

nand_chip.nand_deselect_chip = s3c2410_nand_deselect_chip;

nand_chip.write_cmd = s3c2410_write_cmd;

nand_chip.write_addr = s3c2410_write_addr;

nand_chip.read_data = s3c2410_read_data;

}

else

{

nand_chip.nand_reset = s3c2440_nand_reset;

nand_chip.wait_idle = s3c2440_wait_idle;

nand_chip.nand_select_chip = s3c2440_nand_select_chip;

nand_chip.nand_deselect_chip = s3c2440_nand_deselect_chip;

nand_chip.write_cmd = s3c2440_write_cmd;

#ifdef LARGER_NAND_PAGE

nand_chip.write_addr = s3c2440_write_addr_lp;

#else

nand_chip.write_addr = s3c2440_write_addr;

#endif

nand_chip.read_data = s3c2440_read_data;

s3c2440nand->NFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4);

s3c2440nand->NFCONT = (1<<4)|(1<<1)|(1<<0);

}

nand_reset();

}

void nand_read(unsigned char *buf, unsigned long start_addr, int size)

{

int i, j;

#ifdef LARGER_NAND_PAGE

if ((start_addr & NAND_BLOCK_MASK_LP) || (size & NAND_BLOCK_MASK_LP)) {

return ;

}

#else

if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {

return ;

}

#endif

nand_select_chip();

for(i=start_addr; i < (start_addr + size);) {

write_cmd(0);

write_addr(i);

#ifdef LARGER_NAND_PAGE

write_cmd(0x30);

#endif

wait_idle();

#ifdef LARGER_NAND_PAGE

for(j=0; j < NAND_SECTOR_SIZE_LP; j++, i++) {

#else

for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {

#endif

*buf = read_data();

buf++;

}

nand_deselect_chip();

return ;

}

This long string of red code is the initialization of Nand Flash. We can carefully analyze the control register of Nand.

Looking at the code again, we can jump from head.s to the gray part in nand.c;

1) A judgment between S3C2410 and S3C2440

2) Define a structure

{

nand_chip.nand_reset = s3c2440_nand_reset;

nand_chip.wait_idle = s3c2440_wait_idle;

nand_chip.nand_select_chip = s3c2440_nand_select_chip;

nand_chip.nand_deselect_chip = s3c2440_nand_deselect_chip;

nand_chip.write_cmd = s3c2440_write_cmd;

#ifdef LARGER_NAND_PAGE

nand_chip.write_addr = s3c2440_write_addr_lp;

#else

nand_chip.write_addr = s3c2440_write_addr;

#endif

nand_chip.read_data = s3c2440_read_data;

s3c2440nand->NFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4);

s3c2440nand->NFCONT = (1<<4)|(1<<1)|(1<<0);

}

*The structure is defined above, and the right column contains the functions that can be called in s3c2440;

*In the setup sequence: [NFCONF] register

Enable NAND Flash controller, initialize ECC, and disable chip select: [NFCONT] register

(I think it's good to understand it. I actually went to look at the timing. The teacher didn't explain it clearly. I guess it's the default value.)

【NFCONF】

【NFCONT】

Keywords：ARM Nand Flash Reference address：ARM Nand Flash Control

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