Porting ucosII to STM32F103ZE (Part 1)

1. Development environment:
1.         Development environment:     keil uvision4 MDK4.12 (windows XP)
MDK is RealView MDK (Microcontroller Development kit), which is the latest software development tool for various embedded processors launched by ARM. RealView  MDK  integrates the most advanced technologies in the industry, including uVision4 integrated development environment and RealView compiler. It supports ARM7, ARM9 and the latest Cortex-M3/M1/M0 core processors, automatically configures startup code, integrates Flash burning module, powerful Simulation device simulation, performance analysis and other functions. Compared with ARM's previous toolkit ADS, the latest version of RealView compiler can improve performance by more than 20%.
Outstanding features of RealView MDK:
Rookie's Arabian Flying Carpet - Startup Code Generation Wizard, Automatic Boot, Rapid Progress
The startup code is closely integrated with the system hardware and must be written in assembly language, which makes it difficult for many engineers to cross multiple thresholds. RealView MDK's µVision3 tool can help you automatically generate perfect startup code and provide a graphical window for you to modify easily. Whether for beginners or experienced development engineers, it can greatly save time and improve development efficiency.
Experts are better without swords - software simulator, software development process completely separated from hardware
RealView MDK's device simulator can simulate the entire target hardware , including fast instruction set simulation, external signal and I/O simulation, interrupt process simulation, all peripheral device simulation on the chip, etc. Development engineers can start software development and debugging without hardware, so that software and hardware development can be carried out simultaneously, greatly shortening the development cycle. General ARM development tools only provide instruction set simulators and can only support ARM core simulation debugging.
Experts' Halley telescope - performance analyzer, see farther, see more detailed, see more clearly
RealView MDK's performance analyzer is like a Halley telescope, allowing you to see farther and more accurately. It helps you view code coverage, program running time, function call count and other high-end control functions, and guides you to easily optimize code and become an embedded development expert. Usually these features are only available with expensive trace tools that cost thousands of dollars.
The industry's best compiler , RealView compiler, has smaller code and higher performance.
2.         Processor:         STM32F103ZET6 (Shenzhou III board)
3.         OS version:        uC/OS-II   V2.86
4.         Peripheral library version: STM32F10x_StdPeriph_Lib_V3.5.0
5.         Source code download:
1)         Download the latest version of the stm32 standard peripheral library from the st company website, version V3.5.0 (2012-11-16)
http://www.st.com/internet/com/SOFTWARE_RESOURCES/SW_COMPONENT/FIRMWARE/stm32f10x_stdperiph_lib.zip
2)         Download uC/OS-II       V2.86:
First go to the micrium website to register an account
http://micrium.com/page/home
and then log in and download
http://micrium.com/newmicrium/uploads/file/appnotes/secure/Micrium-ST-uCOS-II-LCD-STM32.exe
2.        Hardware resource introduction:
1.      Introduction:
STM32F103ZET6 is the most advanced configuration chip of STM32F103 series, a 32-bit processor with cortex-M3 core (internal data path, registers, and memory are all 32 bits), adopts Harvard structure, 72M main frequency, LQFP144 package, and has 512K flash and 64K SRAM on chip. Genealogy of the main product series of STM32 family 2.  Instruction system: Cortex-M3 only uses 32-bit thumb2 instructions. With support for 16-bit and 32-bit thumb-2 instruction sets, the cortex-M3 does not need to switch back and forth between thumb and ARM, especially when using large conditional nesting and performing complex operations, the cortex-M3 is much more efficient than the older generation ARM7. 3.  Register group: The Cortex-M3 processor has a register group of R0-R15, of which R13 is used as the stack pointer SP. There are two SPs, but only one can be seen at the same time. This is the so-called "banked" register. R0-R12 are 32-bit general registers used for data operations. But note: most 16-bit Thumb instructions can only access R0-R7, while 32-bit Thumb-2 instructions can access all registers. The Cortex-M3 has two stack pointers, but they are banked, so only one of them can be used at any time. Main stack pointer (MSP): The default stack pointer used after reset, used for the operating system kernel and exception handling routines (including interrupt service routines) Process stack pointer (PSP): Used by the user's application code. The lowest two bits of the stack pointer are always 0, which means that the stack is always 4-byte aligned. Registers and their functions: xPSR  records the ALU flags (0 flag, carry flag, negative flag, overflow flag), execution status, and the interrupt number currently being serviced PRIMASK  disables all interrupts - of course, non-maskable interrupts (NMI) are ignored. FAULTMASK 



 

    




 
    

  







   
   
 Disable all faults - NMI is still unaffected, and the disabled faults will "visit",
BASEPRI     disables all interrupts whose priority is not higher than a specific value.
CONTROL      interrupt mask register group has two functions:
a. Define the privilege level; b. Select which stack pointer is currently used.
4.      Operation mode and privilege level:
Cortex-M3 processor process has two processor modes and two privileged operations.
The two modes are handler mode and thread mode, which are mainly used to distinguish between the code of ordinary applications and the code of exception service routines (including the code of interrupt service routines). The
two privilege levels are privileged level and user level, which are used to provide a storage access protection mechanism so that ordinary user program code cannot accidentally or maliciously perform critical operations. UCSII does not distinguish between privileged level and user level. The program always works at the privileged level, so the switching of the two stack pointers is fully automatic and is handled by hardware when entering and exiting the exception service routine. 5.  Memory Mapping: Compared with the traditional ARM architecture, the memory system of CM3 has undergone a complete transformation: First, its memory mapping is predefined, and it also specifies which location uses which bus. Second, the memory system of CM3 supports the so-called "bit-band" operation. Through it, atomic operations on a single bit are realized. Bit-band operations are only applicable to some special memory areas. http://blog.sina.com.cn/s/blog_abd39cc70101ci44.html Third, the memory system of CM3 supports unaligned access and mutually exclusive access. These two features did not come out until ARMv7-M. Finally, the memory system of CM3 supports both little-endian configuration and big-endian configuration. CM3 has only a single fixed memory mapping. This greatly facilitates the porting of software between various CM3 microcontrollers. Some locations in the memory space are used for private peripherals such as debugging components. This address segment is called the "private peripheral area." The components of the private peripheral area include: 1)  Flash address reload and breakpoint unit (FPB) 2)  Data watchpoint unit (DWT) 3)  Instrumented trace macrocell (ITM) 4)  Embedded trace macrocell (ETM) 5)  Trace port interface unit (TPIU)  ROM table CM3's address space is 4GB, and the program can be executed in the code area, internal SRAM area, and external RAM area. However, because the instruction bus and data bus are separate, it is ideal to put the program in the code area so that instruction fetch and data access each use their own bus and run in parallel. Cortex-M3 predefined memory map CM3 defines 4 attributes for memory access in addition to the memory map, namely:  Bufferable  Cacheable  Executable  Sharable [page] 6.  Bus interface: Cortex-M3 uses a 3-stage pipeline, namely: instruction fetch, decode, and execute. Detailed block diagram Five buses: I-Code bus, D-Code bus and system bus, external private peripheral bus and debug access port bus 7.  Exception Cortex-M3 exception type: Cortex-M3 exception types are divided into two types, namely system exceptions (numbered 1-15, 0 means no exception is running) and external interrupts (greater than or equal to 16). In principle, CM3 supports 3 fixed high priorities and up to 256 levels of programmable priority. The last 240 are external interrupts, that is, "unexpected emergencies", which come from various on-chip peripherals and external peripherals, and are asynchronous, while the first 15 exceptions are generated by CM3 internal activities and are synchronous to CM3. In NVIC, each interrupt has a priority configuration register (1 byte) to configure the priority of the interrupt. However, not every bit of this register is used, and the chips produced by different manufacturers are different. For example, STM32 uses 4 bits, which means that stm32 supports 16 programmable priorities. Note that this register is aligned to the MSB, so the priority configuration register bits 7:4 of each interrupt of stm32 are valid, and bits 3:0 are invalid. "STM32_RM_CH_V10_1 All Models Chinese Reference Manual" 130 Cortex-M3 Exception Type Cortex-M3 Interrupt Priority: For priority, CM3 is divided into preemption priority and sub-priority. The priority grouping (10:8) of the application interrupt and reset control register (AIRCR) in the NVIC describes how to divide the preemption priority and sub-priority. (See the data sheet for details) Cortex-M3 exception vector table Vector table: When an exception occurs and it is to be responded to, CM3 needs to locate the entry address of its service routine, which is stored in the exception vector table. Address 0 is where the boot code is stored, usually mapped to Flash or ROM devices, and their values ​​must not be changed at runtime. However, in order to support dynamic retransmission of interrupts, CM3 allows vector table relocation—locating different vectors starting from other addresses. The area corresponding to these addresses can be the code area, but more often in the RAM area. The entry address of the vector can be modified in RAM. A register in NVIC is called "Vector Table Offset Register" (VTOR) (at address 0xE000_ED08). By modifying its value, the vector table can be relocated. SVC and PendSV SCV (system service call, also referred to as system call) and PendSV (suspendable system call) are mostly used in software development on operating systems. SVC is used to generate call requests for system functions. For example, the operating system usually does not allow user programs to directly access hardware, but instead provides some system service functions to allow user programs to issue call requests to system service functions through SVC. It is mainly used for operating systems that are divided into privileged and user levels. ucosii does not distinguish between privileged and user levels. This can be deleted during porting.
  


    







    
    
    
    
    


  







    

  

 
  

                           
    





  




  



  

 


PendSV, a suspendable system call, can be suspended like a normal interrupt. PendSV is generally used in context switching, that is, task switching, and is the most important interrupt in the ucosii porting process. There are two main points:
a.  When the PendSV interrupt occurs, it is generated by manually writing 1 to the PendSV suspension register of the NVIC (written by the OS).
b.  The PendSV interrupt priority must be set to the lowest.
8.      NVIC and interrupt control
NVIC, the vector interrupt controller, is an inseparable part of the cortex-M3 and is tightly coupled with the core logic. The registers of the NVIC are accessed in a memory-mapped manner. In addition to the control registers and the control logic for interrupt processing, it also contains registers related to the MPU, SysTick timer, and debug control. The access address of the NVIC is 0xE000_E000. (See the data sheet for details)
Each external interrupt is "registered" in the following registers of NVIC:
Ø  Enable and disable registers
Ø  Suspend and "unsuspend" registers
Ø  Priority register
Ø  Active status register
In addition, the following registers also have a significant impact on interrupt processing:
Ø  Exception mask register
Ø  Vector table offset register
Ø  Software triggered interrupt register
Ø  Priority grouping bit field
9.      Interrupt behavior:
When CM3 starts to respond to an interrupt:
1. xPSR, PC, LR, R12 and R3-R0 are pushed to the stack;
2. Vector is taken;
3. Stack pointer MSP/PSP is selected, stack pointer SP is updated, link register LR is updated, and program counter PC is updated.
For porting ucosii, it is necessary to pay attention to 1,3   
nested interrupts:
CM3 core and NVIC have built-in full support for interrupt nesting. There is no need to use assembly to write wrapper code. Just pay attention to the interrupt nesting not being too deep.
10.    For other information, please refer to the data sheet. For example, for STM32F10x modules, such as power control, DMA controller, ADC and DAC, timer, watchdog and window watchdog, static memory controller (FSMC), USB, controller area network CAM bus, synchronous asynchronous transceiver, etc., please refer to the stm32F10x data sheet.