MSP430 Learning Notes (Part 2)

1. Test voltage generator

All ADC and DAC modules require a reference signal, which is what we often call Vref+, Vref-.

The ADC12 module of MSP430 has an internal reference power supply. The internal reference power supply is started by controlling the REFON signal and

REF2_5V controls the internal reference power supply to generate 1.5V or 2.5V Vref+.

Finally, the reference voltage Vr+ and Vr- of the ADC module converter are set in 6 combinations through SREF_x:

Vr+ can be selected between AVcc (system analog power), Vref+ (internal reference power), Veref+ (external input reference power),

Vr- can be between AVss (system analog ground), Vref-/Veref- (internal or external reference power supply).

2. Main features of DC12:

n   12-bit conversion accuracy, 1-bit nonlinear error, 1-bit nonlinear integral error

n   Multiple clock sources for ADC12 module, with its own clock generator

nBuilt- in   temperature sensor

n   TimerA/TimerB hardware trigger

n 8 external channels and 4 internal channels

nBuilt   -in reference voltage source and 6 reference voltage combinations

n 4 modes of analog-to-digital conversion

n   16-bit conversion buffer

n   ADC12 is turned off to support ultra-low power consumption

n   Fast speed, up to 200Kbps

nAutomatic   scanning

n   DMA Enable

3. DC12 register

4. ADC12CTL0    conversion control register 0

ADC12SC: sampling conversion control bit (related to SHP, ISSH, ENC)

  When ENC=1 and ISSH=0:

  When SHP=1: When ADC12SC changes from 0 to 1, A/D conversion is started, and ADC12SC automatically resets after the conversion is completed

  When SHP=0: ADC12SC is sampled when it is at high level, and ADC12SC resets to start a conversion

  Among them, ENC=1 means conversion is allowed, ISSH means the input signal is the same phase input signal,

  SHP=1 means the  sampling signal SAMPCON comes from the sampling timer.

  SHP=0 means that SAMPCON sampling is directly controlled by ADC12SC.

  Note: When the software starts an A/D conversion, ADC12SC and ENC must be set in one statement.

ENC: Conversion enable bit

  0   ADC12 is in initial state, A/D conversion cannot be started

  1The   first conversion is initiated by the rising edge of SAMPCON

  Notice:

  [1] In the case of CONSEQ=0 (single-channel single conversion), when ADC12BUSY=1,

  ENC=0 will end the conversion process and get an error result.

  [2] In the case of CONSEQ≠0 (non-single-channel single conversion), when ADC12BUSY=1,

  If ENC=0, the conversion ends normally and the correct result is obtained.

ADC12TVIE: Conversion time overflow interrupt enable (multiple sampling requests)

  If another sampling request is received before the current conversion is completed, an interrupt will be generated if ADC12TVIE allows it.

  0   allows an interrupt to be generated when a conversion time overflow occurs

  1   Disable interrupt when conversion time overflow occurs

ADC12OVIE: Overflow interrupt enable (ADC12MEMx write multiple times)

  When ADC12MEMx has not been read out, and new data is required to be written into ADC12MEMx,

  If enabled, an interrupt will be generated

  0   Enable overflow interrupt

  1   Disable overflow interrupt

ADC12ON: ADC12 core control

  0   Turn off ADC12 core to achieve low power consumption

  1.   Enable ADC12 core

REFON: Internal reference voltage generator control

  0   turns off the internal reference voltage generator

  1   Turn on the internal reference voltage generator

REF2_5V: internal reference voltage selection 1.5V/2.5V

  0   Select 1.5V internal reference voltage

  1   Select 2.5V internal reference voltage

MSC: Multiple sampling/conversion control bit

  When SHP=1, CONSEQ≠0, the MSC bit will take effect

  0   Each conversion requires the rising edge of the SHI signal to trigger the sampling timer

  1   The first conversion requires the rising edge of the SHI signal to trigger the sampling timer.

  Each subsequent conversion is performed immediately after the previous conversion is completed.

SHT0x: Sample-and-hold time control for channels 0 to 7

  Defines the relationship between the conversion sampling timing and the sampling clock in ADC12MEM0~7

  The shorter the holding time, the faster the sampling speed, which reflects the obvious voltage fluctuation.

 Tsample = 4 × TADC12CLK × N (when N < 13, N = 2n, when n > 13, N = 256)

SHT1x: Sample-and-hold time control for 8 to 15 channels

  Defines the relationship between the conversion sampling timing and the sampling clock in ADC12MEM8~15

  The shorter the holding time, the faster the sampling speed, which reflects the obvious voltage fluctuation.

 Tsample = 4 × TADC12CLK × N (when N < 13, N = 2n, when n > 13, N = 256)

5. ADC12CTL1    conversion control register 1

CSTARTADD: Single channel mode conversion channel / multi-channel mode guard channel

  Defines the starting address for a single conversion or the first address for a sequential channel conversion.

SHSx: Sampling trigger source selection

  0   ADC12SC

  1   TimerA.OUT1

  2   TimerB.OUT1

  3   TimerB.OUT2

SHP: Sampling signal SAMPCON selection

  0   SAMPCON signal comes from the sampling trigger input signal

  1   The SAMPCON signal comes from the sampling timer and is triggered by the rising edge of the sampling input signal.

ISSH: Sampling input signal in the same direction/opposite direction

  0   sampling signal is the same phase input

  1   The sampling signal is the inverting input

ADC12DIVx: ADC12 clock division control

  ADC12 clock source frequency division factor selection bit, the frequency division factor is (x+1)

ADC12SSELx: ADC12 clock selection

  0   ADC12OSC (ADC12 internal clock source)

  1   ACLK

  2   MCLK

  3   SMCLK

COMSEQx: Conversion Mode

  0Single   channel single conversion

  1   Sequence channel single conversion

  2Single   channel multiple conversions

  3-   sequence channel multiple conversion

ADC12BUSY: busy flag (converting...)

  0   means no active operation of ADC12

  1   ADC12 is busy during sampling/conversion.

6. ADC12MCTLx    channel storage control register

EOS: multi-channel conversion end channel flag

  0   The sequence has not ended

  1The   last conversion in the sequence

SREFx: Reference source selection

  0   Vr+=AVcc,    Vr-=AVss

  1   Vr+=Vref+,   Vr-=AVss

  2,3   Vr+=Veref+, Vr-=AVss

  4   Vr+=AVcc,    Vr-=Vref-/Veref-

  5   Vr+=AVcc,    Vr-=Vref-/Veref- 

  6,7   Vr+=AVcc,    Vr-=Vref-/Veref-

INCHx: corresponding analog voltage input channel

  0~7    A0~A7

  8     Veref+

  9     Veref-/Vref-

  10    on-chip temperature sensors

  11~15   (AVcc-AVss)/2

7. ADC12IFG    interrupt flag register

ADC12IFGx: interrupt flag

Corresponding to ADC12MEMx, when the A/D conversion is completed, the data is stored in ADC12MEMx, and the ADC12IFGx flag is set.

ADC12IEx: Interrupt enable bit

Corresponding to ADC12IFGx, if ADC12IEx is allowed, the interrupt service routine of ADC12 will be entered when ADC12IFGx is set.

8. C12 conversion mode

The ADC12 module provides a total of 4 conversion modes

Single channel   single conversion

n   Sequential Channel Single Conversion

Single channel   multiple conversion

n-   sequence channel multiple conversion