TQ2440 National Embedded Academy gboot-turn off watchdog

 1. Many people do not understand the meaning of watchdog, so what exactly is a watchdog?

The watchdog, also known as the watchdog timer, is a timer circuit. It usually has one input, called kicking the dog or servicing the dog, and one output to the RST terminal of the MCU. When the MCU is working normally, it outputs a signal to the dog feeding terminal at regular intervals to clear the WDT. If the dog is not fed for a specified period of time (usually when the program is running away), the WDT timing is exceeded, and a reset signal will be given to the MCU to reset the MCU. Prevent the MCU from crashing. The function of the watchdog is to prevent the program from looping or running away.
Working principle of the watchdog: After the system is running, the watchdog counter is started, and the watchdog starts counting automatically. If the watchdog is not cleared after a certain period of time, the watchdog counter will overflow, causing a watchdog interrupt and causing the system to reset. Therefore, when using a chip with a watchdog, pay attention to clearing the watchdog.

Watchdogs are divided into hardware watchdogs and software watchdogs. The hardware watchdog uses a timer circuit whose timing output is connected to the reset terminal of the circuit. The program clears the timer within a certain time range (commonly known as "feeding the dog"). Therefore, when the program works normally, the timer can never overflow, and no reset signal can be generated. If the program fails and the watchdog is not reset within the timing period, the watchdog timer overflows to generate a reset signal and restart the system. The principle of the software watchdog is the same, except that the timer on the hardware circuit is replaced by the internal timer of the processor. This can simplify the hardware circuit design, but it is not as reliable as the hardware timer. For example, if the internal timer of the system fails, it cannot be detected. Of course, there are also dual timers that monitor each other, which not only increases system overhead, but also cannot solve all problems, such as interrupt system failure causing timer interrupt failure.

The watchdog itself is not used to solve the problems that occur in the system. The faults found during the debugging process should be checked and corrected for the errors in the design itself. The purpose of adding a watchdog is to automatically restore the system to normal working state without human intervention when the system freezes due to some potential program errors and harsh environmental interference. The watchdog cannot completely avoid the losses caused by faults. After all, there is a period of idleness from the discovery of the fault to the system reset and recovery. At the same time, some systems also need to protect the on-site data before resetting and restore the on-site data after restarting, which may also require a software and hardware cost.

Simply put, a watchdog is a monitoring mechanism that makes judgments on abnormalities.

2. TQ2440 watchdog

In the S3C2440 specification, there is a section dedicated to the watchdog, namely WATCHDOG TIMER, which is introduced as follows:

OVERVIEW
The S3C2440A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions，such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles.
FEATURES
— Normal interval timer mode with interrupt request
— Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 (time-out).

From the above paragraph, we can see that the clock signal used by the watchdog is the signal source of PCLK. Of course, curious students will definitely ask what PCLK is. The specific details of PCLK will be introduced in the system clock. Simply put, PCLK is the system clock 12MHZ (or it may be 24MHZ) obtained through a phase-locked loop. The frequency of PCLK is an integer multiple of the system clock, which will be introduced later.

2. Working mechanism of watchdog

This picture is also found in the specification book. It can be seen that after PCLK is set by the WTCON control register, it enters MUX, then WTDAT, and finally WTCNT data register. That is to say, when the watchdog is working, the watchdog will count and compare the count value with the value of the data register. If it overflows, an interrupt will be generated, that is, reset. Therefore, before turning on the watchdog, the watchdog data register WTDAT must be initialized. This principle is also introduced in the specification book, as follows

WTDAT & WTCNT
Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). In this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts.

3. Turn off the watchdog

When it comes to really turning off the watchdog, how can we turn off the watchdog? Of course, through the watchdog control register WTCON, continue to read the following

Here we mainly introduce the watchdog control register WTCON. The other two registers will not be introduced for the time being and will be shared with you when they are used.

First, we see the address of the WTCON register 0x53000000, and then the last line of the table Reset enable/disable = WTCON[0]. That is, the last bit of WTCON controls whether the watchdog is turned on or off, 1: on; 0: off.

Here is the code to turn off the watchdog:

#define pWTCON 0x53000000  //macro definition pWTON: 0x53000000, looks familiar, yes, this is the address of the watchdog WTCON
disable_watchdog:   //subroutine entry function

  ldr r0, =pWTCON    //Load 0x53000000 into the r0 register
  mov r1, #0x0           //Transfer 0 to the r1 register
  str r1, [r0]                 //Load the value of the r1 register into the r0 storage address register, which is 0x53000000
  mov pc, lr                //Call the pc pointer to return.