MSP430--Timer B

1. Timer B module:

TimerB is mostly the same as TimerA, except that a latch is added to the capture/compare unit of Timer B.

The difference between the two:

(1) The count length of Timer B is programmable to 8, 10, 12, or 16 bits, which is configured by the two bits CNTLx in the TBCTL register, while the count length of Timer A is fixed at 16 bits;

(2) Timer B does not implement the SCCI function bit in Timer A;

(3) The capture/compare register function of TimerB in compare mode is different from that of TimerA, and a capture compare latch is added;

(4) In some chip models, TimerB output realizes high impedance output;

(5) The principle of the comparison mode is different: the CCRx register in TimerA stores the data to be compared with TAR, while the CCRx register in TimerB stores the data to be compared, but it is not directly compared with the timer TBR. Instead, the data in CCRx is latched into the corresponding latch, and then compared with TBR by the latch. The time of transmitting data from the capture/compare register to the comparison latch is also programmable. It can be transmitted immediately after writing to the comparison capture register, or a timer can be used to trigger the transmission.

(6) TimerB supports multiple synchronous timing functions, multiple comparison capture functions and multiple waveform output functions (PWM waves). Moreover, through two-level buffering of comparison data, multiple PWM waves can be updated synchronously.

2. Logical structure diagram of TimerB: The logical structure of Timer B is basically the same as that of Timer A.

3. Registers of timer B:

For the configuration process of the relevant bits of the register, refer to Timer A and the data manual.

4. Comparison function of timer B

When timer B operates in compare mode, the data is written into the capture compare latch TBCCRx. When the load event determined by the CLLDx bit in TBCCTLx occurs, the data in TBCCRx is automatically transferred to the compare register.

5. Routine provided by TI:

//
//   // 
//
//                MSP430F149
//             -----------------
//         /||               XIN|-
//          | |                  | HF XTAL (455k - 8MHz)
//          --|RST           XOUT|-
//            |                  |
//            |          P4.1/TB1|--> CCR1 - 75% PWM
//            |          P4.2/TB2|--> CCR2 - 25% PWM
//
/ /   M. Buccini
//   Texas Instruments Inc.
//   Feb 2005
//   Built with IAR Embedded Workbench Version: 3.21A
//**************************** *************************************************** *****

#include   

void main(void)
{
  volatile unsigned int i;
  WDTCTL = WDTPW +WDTHOLD;                   // Stop WDT

//System clock initialization
  BCSCTL1 |= XTS;                            // ACLK= LFXT1 = HF XTAL

  do
  {
  IFG1 &= ~OFIFG;                            // Clear OSCFault flag
  for (i = 0xFF; i > 0; i--);                // Time for flag to set
  }
  while ((IFG1 & OFIFG));                    // OSCFault flag still set?

  BCSCTL2 |= SELM_3;                         // MCLK= LFXT1 (safe)

//io port initialization
  P4DIR |= 0x06;                             // P4.1 and P4.2 output
  P4SEL |= 0x06;                             // P4.2 and P4.2 TB1/2 otions

//Configuration of timer B
  TBCCR0 = 128;                              // PWM Period/2
  TBCCTL1 = OUTMOD_6;                        // CCR1 toggle/set
  TBCCR1 = 32;                               // CCR1 PWM duty cycle
  TBCCTL2 = OUTMOD_6;                        // CCR2 toggle/set
  TBCCR2 = 96 ;                               // CCR2 PWM duty cycle
  TBCTL = TBSSEL_1 + MC_3;                   // ACLK, up-down mode

  _BIS_SR(CPUOFF);                           // Enter LPM0
}