MCU Control Register - MCUCR
Four trigger modes of external interrupt:
ISCx1 ISCx0 Description
0
0
1
1
Bit3, bit2, bit1, bit0 are the setting bits for interrupt 1 and 0 respectively;
MCU Control and Status Register - MCUCSR;
7
JTD ISC2 – JTRF WDRF BORF EXTRF PORF
Bit6 – ISC2: Interrupt 2 trigger mode control bit
Asynchronous external interrupt 2 is activated by external pin INT2 if the I flag in the SREG register and the corresponding interrupt mask bit in the GICR register are set. If ISC2 is written as 0, the falling edge of INT2 activates the interrupt. If ISC2 is written as 1, the rising edge of INT2 activates the interrupt.
General Interrupt Control Register - GICR
INT1 INT0 INT2 – – – IVSEL IVCE
Bit 7 – INT1: Enable external interrupt request 1,
Bit 6 – INT0: Enable external interrupt request 0,
Bit
General Interrupt Flag Register - GIFR
7
INTF1 INTF0 INTF2 – – – – –
Bit 7 – INTF1: External interrupt flag 1;
Bit
Bit
Note that when entering certain sleep modes with the INT2 interrupt disabled, the input buffer for this pin will be disabled. This results in a logic change in the INTF2 flag setting signal.
Rising edge trigger
Falling edge trigger
Any level change trigger
Low level trigger
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