8086 instruction system --- control transfer instructions (Part 2)

　　This group of instructions is used to control the repeated execution of a section of program (called loop body) in the program with loop structure. The redirection address of the loop is represented by a label in the assembly instruction, while the displacement is given in the machine instruction. Therefore, when executing the loop instruction, if the loop condition is met, the CPU calculates the redirection address: (IP) current + 8-bit displacement → (IP), that is, the loop is implemented.

　　If the loop condition is not met, the loop is exited and the program continues to execute sequentially.
　　The loop instructions are all instructions in short transfer format, that is, the displacement is represented by an 8-bit signed number, and the redirection address is within the range of -128 to +127 bytes relative to the current IP value.

　　For the conditional loop instructions LOOPZ (LOOPE) and LOOPNZ (LOOPNE), in addition to testing the number of loops in CX, the value of ZF is also used as a necessary condition for the loop. Therefore, it is necessary to pay attention to placing the conditional loop instruction immediately after the instruction that forms ZF.

　　In the program structure with multiple loops, if each layer of loops is controlled by loop instructions, it is necessary to pay attention to the preservation and restoration of the loop count value in CX.
The loop instructions do not affect the conditional code.

　　LOOP label loop (loop)
　　executes the operation: ① (CX)←(CX)－1
　　　　　　　② If (CX)≠0, then (IP)←(IP) current + displacement, otherwise the loop ends

　　LOOPZ/LOOPE label when it is zero/equal (loop while zero，or equal)
　　executes the operation: ① (CX)←(CX)－1
　　　　　　　② If ZF=1 and (CX)≠0, then (IP)←(IP) current + displacement, otherwise the loop ends

　　LOOPNZ/LOOPNE label when it is not zero/unequal (loop while nonzero，or not equal)
　　executes the operation: ① (CX)←(CX)－1
　　　　　　　② If ZF=0 and (CX)≠0, then (IP)←(IP) current + displacement, otherwise the loop ends

    Example Write a program to add two data blocks BLOCK1 and BLOCK2 and store the result in BLOCK2.
　　 　　　　DATA SEGMENT
　　　　　　 BLOCK1 DW 100 DUP(?)
　　　　　 　BLOCK2 DW 100 DUP(?)
　　 　　　　DATA ENDS
　　 　　　　; - - - - - - - - - - - - - - - - -
　 　　　　　CODE SEGMENT
　　 　　　　ASSUME CS:CODE,DS:DATA,ES:DATA
　　　　START:MOV AX,DATA
　　　　　　　MOV DS,AX ; initialize the data segment
　　　　　　　MOV ES,AX ; initialize the extra segment
　　　　　　　CLD ; DF=0 for autoincrement
　　　　　　　MOV CX,100 ; load the counter
　　　　　　　MOV SI,OFFSET BLOCK1 ; address of block1
　　　　　　　MOV DI,OFFSET BLOCK2 ; address of block2
　　 　NEXT: LODSW ; load the data of block1 into AX
　　　　　　　ADD AX,ES:[DI] ; add the data of block2 to AX
　　　　　　　STOSW ; store the sum to block2
　　　　　　　LOOP NEXT ; repeat 100 times
　　　　　　　MOV AX,4C00H ; return to DOS
　　　　　　　INT 21H
　　 　CODE ENDS
　　　　　　　END START

　  4 ​​Subroutine call and return instructions

　　A subroutine is a very important computer programming structure. It is stored in the memory and can be called repeatedly by one or more calling programs (main programs). The main program uses the CALL instruction to call a subroutine, and the RET instruction is used when the subroutine returns to the main program. Since the calling program and the subroutine can be in the same code segment or in different code segments, the CALL instruction and the RET instruction also have two formats: near call and near return and far call and far return.

　⑴ CALL NEAR PTR SUBPROUT Near call
　　is the default format of the CALL instruction, which can be written as "CALL subrotine". It calls a subroutine (subprocedure) in the same code segment. Therefore, the value of CS does not need to be changed during the call process. The address of the subroutine only needs to be stored in the IP register. The call address in the CALL instruction can be represented by direct and indirect addressing methods.

　⑵ CALL FAR PTR SUBPROUT Far call Far call
　　is applicable to the situation that the calling program (also called main program) and the subroutine are not in the same segment, so it is also called inter-segment call. Like the near call instruction, the addressing mode in the far call instruction can also be direct or indirect.

　⑶ RET return instruction
　　The operation performed by the RET instruction is to pop the return address saved in the stack to complete the function of returning from the subroutine to the calling program.

　　● CALL SUBROUT Intra-segment direct call
　　Execution operation: ① (SP) ← (SP)-2, ((SP)) ← (IP) current
　　　　　　　② (IP) ← (IP) current + 16-bit displacement (in the 2nd and 3rd bytes of the instruction)
　　
　　● CALL DESTIN Intra-segment indirect call
　　Execution operation: ① (SP) ← (SP)-2, ((SP)) ← (IP) current
　　　　　　　② (IP) ← (EA); (EA) is the effective address determined by the instruction addressing mode

　　● CALL FAR PTR SUBROUT Inter-segment direct call
　　Execution operation: ① (SP) ← (SP)-2, ((SP)) ← (CS) current
　　　　　　　　 (SP) ← (SP)-2, ((SP)) ← (IP) current
　　　　　　　② (IP) ← offset address (in the 2nd and 3rd bytes of the instruction)
　　　　　　　　 (CS) ← segment address (in the 4th and 5th bytes of the instruction)

　　● CALL WORD PTR DESTIN Inter-segment indirect call
　　Execution operation:① (SP) ← (SP)-2, ((SP)) ← (CS) current
　　　　　　　　 (SP) ← (SP)-2, ((SP)) ← (IP) current②
　　　　　　　(IP) ← (EA); (EA) is the effective address determined by the instruction addressing mode
　　　　　　　　 (CS) ← (EA+2)

　　From the operation performed by the CALL instruction, it can be seen that the first step is to save the address of the subroutine returning to the calling program in the stack. For intra-segment calls, it is only necessary to store the current value of IP, that is, the address of the next instruction of the CALL instruction, in the stack word unit indicated by SP. For inter-segment calls, saving the return address means storing the current values ​​of CS and IP in two word units of the stack respectively. The

　　second step of the CALL instruction is to turn the program, that is, to give the entry address of the subroutine to IP (intra-segment call) or CS:IP (inter-segment call). For the intra-segment direct method, the displacement of the transfer, that is, the difference between the entry address and the return address of the subroutine, is in the 2nd and 3rd bytes of the machine instruction. For the inter-segment direct mode, the offset address and segment address of the subroutine are in the two words after the opcode. For the indirect mode, the entry address of the subroutine is obtained from the effective address determined by the addressing mode.

　　● RET intra-segment return (near return)
　　execution operation: (IP) ← ((SP)), (SP) ← (SP) + 2

　　● RET inter-segment return (far return)
　　execution operation: (IP) ← ((SP)), (SP) ← (SP) + 2
　　　　　　　(CS) ← ((SP)), (SP) ← (SP) + 2

　　● RET N return with immediate value
　　Execution operation: ① Pop the return address from the stack (the operation is the same as intra-segment or inter-segment return)
　　　　　　　② Modify the stack pointer: (SP) ← (SP) + N

　　The last instruction of the subroutine must be a RET instruction to return to the main program. If it is an intra-segment return, just pop the offset address stored in the stack and store it in IP. If it is an inter-segment return, take the offset address and segment address from the stack and send them to the IP and CS registers.

　　The return instruction with an immediate value, in addition to completing the operation of popping the offset address or the offset address and segment address, also adds an immediate value N to the content of SP to move the stack pointer SP to a new position. The N in the instruction can be a constant or an expression. The return instruction with an immediate value is applicable to the calling rules of C or PASCAL. These rules push parameters into the stack before calling a procedure (subroutine). After the subroutine uses these parameters, if these useless parameters are discarded when returning, a number is included in the RET instruction, which indicates the number of bytes of the parameters pushed into the stack, so that the stack pointer is restored to the value before the parameters are pushed into the stack.

　　Neither the CALL instruction nor the RET instruction affects the conditional code.

  　Example Based on the program listing of the calling program and subroutine below, draw the stack situation before and after the RET instruction is executed. Assume that the initial SS:SP=A000:1000.
　
　　　　0000 B8 001E MOV AX,30
　　　　0003 BB 0028 MOV BX,40
　　　　0006 50 PUSH AX; push data1 into stack
　　　　0007 53 PUSH BX; push data2 into stack
　　　　0008 E8 0066 CALL ADDM; call subroutine
　　　　000B B4 02 MOV AH,2
　　　　… … …
　　　　0071 DM PROC NEAR ; entry point (IP)←0071=000b+0066
　　　　0071 55 PUSH BP ; save BP
　　　　0072 8B E4 MOV BP,SP ; addressing the stack with BP 0074
　　　　8B 46 04 MOV AX,[BP+4] ; get data2 from stack
　　　　0077 03 46 06 ADD AX,[BP+6] ; add data1
　　　　007A CD POP BP ; get back BP
　　　　007B C2 0004 RET 4 ; return and revert SP
　　　　007E ADDM ENDP

 Figure 3 Effects of CALL and RET instructions on the stack

 

　　As shown in Figure 3.12, the two PUSH instructions in the main program push data 30 and 40 into the stack. After the CALL instruction is executed, the return address 000B is pushed into the stack again, and then the program control is transferred to the subroutine ADDM. The PUSH instruction in the subroutine pushes the value of BP into the stack again. At this time, SP points to the top of the stack 0FFA. The MOV instruction transfers 0FFA to BP, making BP a pointer to address the stack data. (BP+4) points to 40, and (BP+6) points to 30. After the data is taken out, the POP instruction is used to restore the original value of BP. At this time, (SP)=0FFC, which is the stack state before the RET 4 instruction is executed. [page]

　　When the RET 4 instruction is executed, the return address is first popped from the stack: (IP)←000B, (SP)←0FFC+2=0FFD, and then, (SP)+4=0FFD+4=1000, resulting in SP skipping the stack data and returning to the original position.

　 5 Interrupt and interrupt return instructions

　INT n Interrupt instruction (interrupt), n is the interrupt type number

　IRET Interrupt return instruction (return from interrupt)

　INTO Overflow interrupt (interrupt type is 4)

　　INT n interrupt instruction (interrupt), n is the interrupt type number
　　Execution operation: ① Push FLAGS into the stack: (SP) ← (SP)－2, ((SP)) ← (FLAGS)
　　　　　　　② Push return address into the stack: (SP) ← (SP)－2, ((SP)) ← (CS)
　　　　　　　　　　　　　　　　　 (SP) ← (SP)－2, ((SP)) ← (IP)
　　　　　　　③ Jump to interrupt handler: (IP) ← (n×4)
　　　　　　　　　　　　　　　　 (CS) ← (n×4＋2)

　 IRET interrupt return instruction (return from interrupt)
　　execution operation: ① Pop return address from the stack: (IP) ← ((SP)), (SP) ← (SP)＋2
　　　　　　　　　　　　　　　 (CS) ← ((SP)), (SP) ← (SP)＋2
　　　　　　　② Pop FLAGS from the stack: (FLAGS) ← ((SP)), (SP) ← (SP)＋2

　　INTO Overflow interrupt (interrupt type is 4)
　　Execute operation: If OF=1 (overflow), then:
　　　　　　　① Push to stack and save FLAGS: (SP) ← (SP)-2, ((SP)) ← (FLAGS)
　　　　　　　② Push to stack and save return address: (SP) ← (SP)-2, ((SP)) ← (CS)
　　　　　　　　　　　　　　　　　 (SP) ← (SP)-2, ((SP)) ← (IP)
　　　　　　　③ Jump to interrupt handler: (IP) ← (4×4)= (10H)
　　　　　　　　　　　　　　　　 (CS) ← (4×4＋2)= (12H)

　　The interrupt instruction is used to call the interrupt routine (also known as interrupt service routine), which is a remote call. The interrupt routines that complete various functions have a number, called the interrupt type number. The entry addresses of various interrupt routines are stored in a table in the order of the interrupt type number, which is called the interrupt vector table. The entry address of each interrupt routine occupies 4 bytes, so its address in the interrupt vector table can be obtained by multiplying the interrupt type number by 4. When executing an interrupt instruction, the stack must first be pushed to save the execution site of the calling program, that is, the value of the flag register and the address of the breakpoint at that time. Then, according to the interrupt type number (n×4), the entry address of the interrupt routine is obtained from the interrupt vector table and sent to IP and CS respectively to realize the function of calling the interrupt routine.

　　The operation of the interrupt return instruction IRET is opposite to that of the INT instruction, that is, the return address and flag bit are taken out from the stack, and then returned to the interrupted program.
The implicit interrupt type number of the INTO instruction is 4, so after saving the breakpoint address and flag bit, the entry address of the interrupt routine is taken out from the two words 10H and 12H of the interrupt vector table, so as to switch to running the interrupt routine.

　　After the INT instruction (including INTO) is executed, IF and TF are set to 0, but other flag bits are not affected.

 

　 6 Processor Control Instructions

　　Processor control instructions include a group of instructions that set flags to 0 or 1, and some instructions that control the processor status.

　  6.1 Flag Processing Instructions

　　This group of instructions respectively set, set, or negate the flags CF, DF, and IF. For example, the operation performed by the CLD instruction is: DF←0; the operation performed by the STD instruction is: DF←1. The

　　flag processing instruction only affects the flag specified by the instruction, and does not affect other flags.

　　　　⑴ Flag processing instructions ⑵ Processor control instructions
　　　　　 CLC CF set to 0 NOP No operation
　　　　　 STC CF set to 1 HLT Stop
　　　　　 CMC CF negation WAIT Wait
　　　　　 CLD DF set to 0 ESC Escape
　　　　　 STD DF set to 1 LOCK Lock
　　　　　 CLI IF set to 0
　　　　　 STI IF set to 1

 

　 6.2 Processor Control Instructions

　　NOP No Operation Instruction (no operation)

　　HLT Halt Instruction (halt)

　　WAIT Wait Instruction (wait)

　　ESC mem Escape Instruction (escape)

　　LOCK Prefix Lock (lock)

　　NOP No operation instruction (no operation)
　　Execution operation: No operation is performed. Its machine code occupies 1 byte unit and the execution time is 3 clock cycles. Therefore, the effect of this instruction is manifested in time and space. In terms of time, it can make the execution of the upper and lower instructions have a little interval, which makes the execution of some instructions, especially the instructions that control the hardware interface, increase reliability because of a little delay. In terms of space, its position can be replaced by other instructions when debugging instructions.

　　HLT Halt instruction (halt)
　　Execution operation: Make the processor stop the execution of software and wait for the arrival of an external interrupt. After the interrupt ends, the processor continues to execute the following program. The purpose of using this instruction is usually to keep the external hardware interrupt and the software system synchronized.

　　WAIT Wait instruction (wait)
　　Execution operation: Test the BUSY/TEST pin of the microprocessor. If BUSY/TEST=1 (indicating not busy) when the WAIT instruction is executed, continue to execute the next instruction. If BUSY/TEST=0 (indicating busy) when the WAIT instruction is executed, the microprocessor waits until the BUSY/TEST pin becomes 1.
　　
　　ESC mem escape instruction (escape)
　　execution operation: mem specifies the storage unit. When the ESC instruction is executed, the instruction or operand is obtained from the memory and sent to the 8087~80387 numerical coprocessor through the bus. The coprocessor can handle numerical operations such as arithmetic operations, function operations, logarithmic operations, etc., and its operation speed is much faster than software written using conventional instructions.

　　LOCK prefix lock (lock)
　　execution operation: LOCK is added before the instruction so that the latch signal LOCK=0 is maintained during the lock instruction to disable the main controller or other system components on the external bus. For example, when LOCK MOV AL, [SI] is executed, the bus is locked until the MOV instruction is executed.

　　2. 8086 instruction system
　　　When learning an instruction, pay attention to the following aspects:
　　　(1) Instruction function - what kind of operation can the instruction perform. Usually the instruction mnemonic is the English abbreviation of the instruction function.
　　　(2) Addressing modes supported by the instruction - the addressing modes allowed by the source operand and destination operand fields in the instruction.
　　　(3) The impact of the instruction on the flag bits - the impact of the instruction on each flag bit after execution. (4
　　　) Special requirements of the instruction - the registers implicitly used or limited to use by the instruction and the parameters that need to be preset.