MSP430 Learning Notes (1) Watchdog

a) Watchdog Timer: Basic timing, performs a controlled system restart when a program error occurs

b) Basic timer: basic timing, supporting software and various peripheral modules to work under low frequency and low power consumption conditions

c) Real-time clock: basic timing, calendar function

d) Timer A: Basic timing, supports multiple timing controls, multiple capture/compare functions and multiple output waveforms (PWM) at the same time, and can support serial communication in hardware

e) Timer B: basic timing, the functions are basically the same as Timer A, but more flexible and powerful than Timer A

2. Watchdog timer:

a) WDT register

a) Counting unit WDTCNT: 16-bit up-counting, the fixed-period pulse signal generated by the clock circuit selected by the MSP430 adds to the counter from the beginning until the count overflows. WDTCNT cannot be accessed directly by software, but must be controlled by the control register WDTCTL of the watchdog timer.

b) Control register WDTCL

  WDTCTL consists of two parts: the upper 8 bits are used as a password, and the lower 8 bits are the control commands for WDT operations.

                  To write the control command to operate WDT, you must first write the correct password. The password is 5AH. Errors will cause

The system is reset. No password is required to read WDTCTL, and it can be read directly. The low byte of the read data is the value of WDTCTL, and the high byte is always 69H.

                                      i. WDTHOLD: stop the watchdog, 1 stop

                                    ii. WDTNMIES: Watchdog NMI (non-maskable interrupt) trigger edge selection. When WDTNMI is 1, modifying this bit generates an interrupt, and when it is 0, it does not generate an interrupt. If this bit is 0, NMI is triggered on the rising edge, and if it is 1, NMI is triggered on the falling edge.

                                   iii. WDTNMI: Watchdog NMI selection, select the function of the RST/NMI pin. When it is 0, it is the reset function, and when it is 1, it is the NMI function.

                                   iv. WDTTMSEL: Watchdog working mode selection, 0 is watchdog mode, 1 is timer mode.

                                    v. WDTCNTCL: When it is 1, the watchdog counter is cleared.

                                   vi. WDTSSEL: Watchdog clock source selection, select SMCLK when it is 0, and select ACLK when it is 1.

                                 vii. WDTISx: Timing output of the watchdog timer, 00 counts 32768, 01 counts 8192, 10 counts 512, 11 counts 64.

c) Interrupt enable register IE1:

                                      i. NMIE: interrupt enable when 1

                                    ii. WDTIE: Watchdog timer enable. This bit is set to 1 when working in timer mode. It is not necessary to set this bit to 1 when working in watchdog mode because other interrupts may occupy this bit.

d) Interrupt flag register IFG1:

                                      i. NMIFG: 1 indicates an interrupt has occurred, 0 indicates no interrupt has occurred. This bit must be cleared by software.

                                    ii. WDTIFG: Watchdog timer interrupt bit. In watchdog mode, it needs to be cleared by software. In timer mode, it will be automatically cleared when an interrupt is processed. When it is 1, there is an interrupt, and when it is 0, there is no interrupt.