S3C6410 Learning——MemoryMap

S3C6410 is different from S3C2440. S3C6410 supports 32-bit physical address space and divides the address space into two parts, one is "storage space" and the other is "peripheral space". The main storage space is accessed through SPINE bus, and its address space is 0x0000,0000~0x6FFF,FFFF. The main storage space is divided into four areas - boot image area, internal memory area, static memory area and dynamic memory area.

The address space of the boot image area is 0x0000,0000~0x07FF,FFFF, but there is no actual memory mapping. The boot image area is mapped to part of the internal storage area or static storage area, and the starting address is fixed at 0x0000,0000.

The internal storage area is for the boot loader to access the internal ROM (internal ROM) and internal SRAM (internal SRAM), also known as Steppingstone. The starting address of each internal memory is fixed. The address space of the internal ROM is 0x0800,0000~0x0BFF,FFFF, but the actual storage space is only 32KB. This area is read-only, and when the boot mode is selected as internal ROM boot, this area should be mapped to the boot image area (boot image area). The address space of SRAM is 0x0C00,0000~0x0FFF,FFFF, but the actual storage space is only 4KB.

The address space of the static storage area is 0x1000,0000~0x3FFF,FFFF. Through this area, SROM, SRAM, NOR Flash, asynchronous NOR interface devices, OneNand Flash and Steppingstone can be accessed. Each area corresponds to a chip select, for example, the address space 0x1000,0000~0x17FF,FFFF corresponds to Xm0CSn[0]. The starting address of each chip select is fixed. Nand flash and CF/ATA cannot be accessed through the static storage area, so if any area corresponding to Xm0CSn[5:2] is mapped to NFCON or CFCON, the address space of the corresponding area will be inaccessible. A special case is that when the area corresponding to Xm0CSn[2] is used for NAND Flash, Steppingstone is mapped to the address space 0x2000,0000~0x27FF,FFFF.

The address space of the dynamic storage area is 0x4000,0000~0x6FFF,FFFF, and DMC1 has the right to use the address space of 0x5000,0000~0x6FFF,FFFF. The starting address of each chip select is configurable.

The peripheral space is accessed through the PERI bus, and its address space is 0x7000,0000~0x7FFF,FFFF. All special function registers can be accessed through this area. If the data comes from NFCON or CFCON, these data are also accessed through the PERI bus.

The memory distribution of the main storage area is as follows:

Please refer to the manual directly for the spatial distribution of peripherals. The above is purely my personal understanding of the chip manual. If there are any omissions, please point them out.