SD16 module in MSP430

The English in the Datesheet was not pleasant to look at, and I suddenly found the SD16 module introduction in the Lierda 430 presentation materials, as well as the MSP430FE42X Chinese reference manual. I summarized it for easy learning, and first came to the structure diagram.
SD16 structure diagram

SD16CTL, ADC control register

Reserved Bit 0 Reserved, always read as 0.

OVIE Bit 1 Overflow interrupt enable, overflow interrupt vector is enabled independently.

                   If a conversion result is written into the ADC memory SD16MEMx, but the previous result has not been read, an overflow occurs.

REFON Bit 2 Turns on the internal reference voltage . If not used, the reference should be turned off to save energy.

               0: Internal reference is off.

                      If an ADC is used, the reference voltage must be supplied externally, otherwise the conversion results are unpredictable.

               1: Internal reference voltage is turned on.

                      Note that the VREF pin needs to be connected to a capacitor .

VMIDON Bit 3 Turn on Vmid buffer.

                     If the intermediate voltage is not used, it should be turned off to save energy. Note that the reference voltage is used as the intermediate voltage.

                 0: Vmid buffer is off.

                 1: Vmid buffer is on.

SSELx Bit 5, 4 Select the clock source.

                 0 (00): MCLK

                 1 (01): SMCLK

                 2 (10): ACLK

                 3(11): External clock

DIVx Bit 7, 6 Select the clock division factor.

                     These bits should not be modified during conversion. If modified during conversion, all channels will perform internal

                    Reset and then restart the conversion.

                  0 (00): Divide by 1

                  1 (01): Divide by 2

                  2 (10): Divide by 4

                  3 (11): Divide by 8

LP Bit8 Low power mode.

                  0: Disable low power mode. The ∑-△ module can run at the maximum specified clock frequency.

                  1: Enable low power mode. The maximum clock frequency of the ∑-△ module is reduced.

Reserved Bits9-15 are reserved and are always read as 0. 

SD16CCTLx, ∑-△ADC channel control register:

GRP bit 0 Grouping.

            0: Not in a group, or the last channel of a group.

            1: Forms a group with the following channels.
                It should be noted that the GRP bit of the last executed channel (i.e. the channel with the highest number) cannot be set, it is always read
            as 0. This feature can be used to monitor the number of executed channels and ensure that the SC bit of the last channel always starts
            the AD conversion of the group.
SC Bit 1 Start conversion.
               This bit is automatically set by the SC bit of the last channel if the channel belongs to a group (i.e. GRP is set)
           . To switch off the conversion of a group of channels, it is sufficient to clear the SC bit of the last channel. But it is also possible to switch off individual channels (except the last channel) by clearing their
           respective . After clearing the SC bit, the ∑-△ ADC
           will complete its clock cycle (asynchronously with the CPU clock), for example, the following may happen - the value in the conversion memory
           may change after the SC bit is cleared, so it is recommended to read the conversion memory before the SC bit is cleared.
           0: Conversion stopped. The Sigma-Delta modulator is powered down and the digital filter is turned off.
           1: Start conversion.
IFG Bit 2 Interrupt flag.
                Set when a new conversion result is completed, automatically cleared after a read operation on the SD16MEMx. The initial setting of the interrupt flag
            can be delayed using the INTDLY bit in the input control register SD16INCTLx.
IE Bit 3 Interrupt enable bit.
DF Bit 4 Data format.
             0: Unipolar (binary offset)
             1: Bipolar (two's complement)
OVIFG Bit 5 Overflow interrupt flag.
                 Overflow occurs if a conversion result is written to the ADC storage register SD16MEMx before the previous conversion result is read.
LSBACC Bit 6 1: The output of the digital filter must have at least 16 valid bits.
             0: The output of the digital filter must have at most 16 valid bits.
LSBTOG Bit 7 Each time SD16MEMx is read, the value of LSBACC is held constant and cannot be changed.
OSR Bit 8, 9 Oversampling rate.
                   These two bits should not be changed during a conversion. If these two bits are changed during a conversion, this channel
               and all other channels in the same group will undergo an internal reset and then restart a conversion.
              0: OSR = 256
              1: OSR = 128
              2: OSR = 64
              3: OSR = 32
SNGL Bit 10 Signal conversion mode selection.
              0: Continuous conversion.
              1: Single conversion.
                 SC is automatically cleared after the interrupt flag IFG is set. Note that the interrupt flag setting can
              be delayed by the INTDLY bit in the input control register SD16INCTLx. It is recommended to use the default setting (delay of three sampling cycles) to ensure that
              the conversion result is completed when the interrupt flag is set.
Reserved Bits 11-15 Reserved, always read as 0.


SD16INCTLx, ∑-△ ADC input control register:

INCHx Bits 2-0 Select different input channels.
                   Changes to these bits in a conversion will affect the next steps of the digital filter. It should be noted that the next two or three digitized values ​​do not exist after
                the change , because the digital filter needs time to set up. This
               situation can be automatically handled by the INTDLY bit.

               0(000): Ax.0

               1(001): Ax.1

               2 (010): Ax.2

               3 (011): Ax.3

               4 (100): Ax.4

               5(101): Ax.5

               6 (110): Ax.6 Temperature sensor

               7 (111): Ax.7 D+ and D- shorted. Allows measurement of the offset produced by the Sigma-Delta modulator.
GAINx bits 5-3 select the gain of the preamplifier
.                    A change of these bits during a conversion affects the next steps of the digital filter. Note that the next two or three digitized values ​​are not available
               after , as the digital filter takes time to set up. This situation
               is automatically handled by the INTDLY bit.

               0 (000): PGA gain = 1

               1 (001): PGA gain = 2

               2 (010): PGA gain = 4

               3 (011): PGA gain = 8

               4 (100): PGA gain = 16

               5 (101): PGA gain = 32

               6 (110): Reserved

                7 (111): Reserved
INTDLYx bits 7-6 The number of samples to delay before the start of a conversion.
                    This allows the digital filter to stabilize before generating a digital value for subsequent processing. If the gain
               (SD16INCTLx GAIN) or the selected input channel (SD16INCTLx INCH) is changed during a conversion,
                the generation of the next interrupt is also delayed according to the selected settings.
                    Note that during the delay, the generation of the interrupt is delayed and the overflow detection is disabled, but
                the contents of the SD16MEMx register will change with the next step of the digital filter.
                0 (00): Delay of three sample cycles (interrupt occurs on the fourth sample cycle)
                1 (01): Delay of two sample cycles (interrupt occurs on the third sample cycle)
                2 (10): Delay of one sample cycle (interrupt occurs on the second sample cycle)
                3 (11): No delay (interrupt occurs on the first sample cycle)
SD16MEMx, ∑-△ ADC Conversion Storage Registers:

ConversionResult bits 15-0 The data format is controlled by the DF bit in the channel register SD16CCTLx and can be either twos complement
                            or binary offset. All other bits are identical in both formats except that the highest bit is
                            simply inverted when compared to the other.

SD16PREx, ∑-△ ADC Preload Register:
   
PreloadValue Bits 7-0 The channel's preload register SD16PREx can be used to preload the digital filter counter.
                                     This counter is responsible for providing the time frame used to average the bit stream from the Sigma-Delta modulator.
SD16IV, Interrupt Vector Register:

SD16IVx Bits 15-0 The Sigma-Delta ADC has an interrupt vector. The interrupt vector register SD16IV assists in handling
                                 multiple interrupt flags.