The Nested Vector Interrupt Controller (NVIC) is a key component in the Cortex-M3 processor. It provides a standard interrupt architecture and excellent interrupt response capabilities for microcontrollers based on Cortex-M3, provides dedicated interrupt entries for more than 240 interrupt sources, and can give each interrupt source a separate priority. Using NVIC, you can achieve extremely fast interrupt response speed. It only takes 12 cycles from receiving an interrupt request to executing the first instruction of the interrupt service. This extremely fast response speed is due to the automatic stack processing mechanism of the Cortex-M3 core, which is implemented by the microcode solidified in the CPU. On the other hand, when interrupt requests appear continuously, NVIC uses a technology called "tail chaining" to enable continuous interrupts to be serviced within 6 clock cycles. During the stacking phase of the interrupt, a higher priority interrupt can complete the action of embedding a low priority interrupt without consuming any additional CPU cycles. I will summarize the details later. Users can set the CPU to automatically enter a low power state and use interrupts to wake it up. The CPU will remain in sleep mode until the interrupt time comes. I will summarize this later.
The Cortex-M3 CPU supports two operating modes: Thread Mode and Handler Mode. It should be noted that both modes have their own independent stacks. This design allows developers to perform more sophisticated programming and better support for real-time operating systems. The
Cortex-M3 processor also includes a 24-bit automatically reloadable timer that can provide a periodic interrupt for the kernel (RTOS).
In terms of instruction sets, ARM7 and ARM9 have two instruction sets (32-bit instruction sets and 16-bit instruction sets), while the Cortex-M3 series processors support the Thumb-2 instruction set. Because the Thumb-2 instruction set combines the Thumb instruction set and the ARM instruction set, it achieves a balance between the performance of the 32-bit instruction set and the code density of the 16-bit instruction set.
Moreover, ARM Thumb-2 is specially designed for C/C++ compiler, which means that the development and application of Cortex-M3 series processors can be completed in the C language environment.
The launch of STM32 microcontrollers marks a major step forward for ST in two main product lines (low-cost main line and high-performance main line). When STM32 was first released, there were 14 different models, divided into two versions: "enhanced" with a maximum CPU clock of 72MHZ and "basic" with a maximum CPU clock of 36MHZ. The built-in Flash of these different STM32 models can reach up to
128KB and the maximum SRAM is 20KB. At the beginning of the release of STM32, versions with larger Flash, RAM and more complex peripherals were already planned. Regardless of the version and model of STM32 devices, they are compatible in pin functions and application software. This allows developers to change device models as needed without changing the PCB when using the STM32 series microcontrollers.
At first glance, the equipment configuration of STM32 is somewhat similar to the familiar 51 single-chip microcomputer in the past. Generally, STM32 is equipped with common peripherals, such as multi-channel ADC, general timer, I2C bus interface, SPI bus interface, CAN bus interface, USB controller, real-time clock RTC, etc. However, each of its external devices has its own unique features. For example, the 12-bit precision ADC has multiple conversion modes and an internal temperature sensor. The STM32 device with dual ADC can also make two ADCs work at the same time, thus deriving more advanced 9 conversion modes; each timer of STM32 has 4 capture comparison units, and each timer can work in conjunction with other timers to generate more precise timing; STM32 has an advanced timer specially designed for motor control, with 6 PWM output channels with programmable dead time, and its emergency brake channel can force the PWM signal output to remain in a predetermined safe state when abnormal conditions occur; the SPI interface contains a hardware CRC unit that supports CRC calculation of 8-bit byte and 16-bit half-word data. It is very useful when accessing data from storage media such as SD or MMC.
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