Design of DDS Sine Signal Generator Using CPLD

　　This article realizes the generation of DDS sinusoidal signal . Due to the fact that the 128 macro units of CPLD are not enough and we don't know how to optimize them, we simply let the buttons, frequency display, and frequency control word be controlled by the single-chip microcomputer, and then the single-chip microcomputer transmits the frequency control word to the CPLD, so that the frequency control is realized. The frequency range of the final sinusoidal signal is 1HZ~30KHZ. The frequency can be stepped by 1HZ or preset by the single-chip microcomputer, or the frequency signal can be automatically swept. At first, the maximum error of the frequency reached more than 2HZ, and I felt that something was wrong. The frequency should be very accurate and there would not be such a large error. Later, it was found that the crystal oscillator was inaccurate and there was a little error. Later, the program was modified to make the maximum output frequency error within 0.1HZ. After these days of hard work, I finally felt a little relieved.

　　This is the VHDL top level module:

　　This is the simulation waveform when k=0011111111111111:

　　The single chip microcomputer controls 6 digital tubes to display the current frequency, and the P1 port is connected to 4 function buttons, namely +, -, select and sweep, and then two 574 chips are used to output the frequency control word to the CPLD. This is all I can do for now due to time constraints.

　　Since it is converted by DAC0832 (conversion time 1us), the crystal oscillator is limited to 1M. The maximum frequency is also limited to 0.5MHZ according to the Nyquist sampling theorem (but the distortion is very large, so it is better to take a smaller one). Finally, the waveform can be filtered.