Design of automatic bad block detection system based on single chip microcomputer FIash memory

With the rapid development of electronic technology, intelligent electronic products can be seen everywhere, such as PCs, mobile phones, PDAs, digital cameras, game consoles, digital TVs, etc., and the core components of such electronic products are often inseparable from memory. Whether it is from the physical structure of the memory, storage capacity, data reading and writing speed, reliability, durability, or the practicality of the product. There are many types. However, for various reasons, more and more electronic products use NAND-type Flash memory with fast data transmission and large capacity. Although NAND-type Flash has many advantages, it has the inevitable bad blocks generated randomly. If the bad blocks cannot be well solved, it will lead to a high failure rate. Therefore, a DSP-based Flash memory bad block automatic detection system is proposed here.

1 System Design

FIG1 is a block diagram of the Flash memory bad block automatic detection system.

This system design uses AT89C51 to automatically detect invalid blocks of NAND Flash memory, obtain bad block information of Flash memory, and prepare for subsequent data storage. This system design includes two parts: hardware circuit and supporting software design. Its hardware circuit mainly consists of four parts: single-chip microcomputer, control, display and memory. The single-chip microcomputer part adopts the conventional minimum system circuit; the control part consists of buttons and external interrupts of the single-chip microcomputer. The button is connected to the ground terminal through a resistor, and the reset button is connected to the power supply terminal; the display part uses the P0 and P1 ports of the single-chip microcomputer to control the 8-bit seven-segment common anode digital tube, the bit selection end is controlled by the P2 port, and the data end is controlled by the Pl; the memory part is connected to the single-chip microcomputer. Due to the level difference, a level converter 74LVX42-45 is required to convert the 5 V voltage output by the single-chip microcomputer to 3 V, and convert the 3V voltage output by the Flash to 5V. The conversion direction is easy to control. The software design part uses the C language of the microcontroller to write the program. After the data is stored in the microcontroller, it is put into an array using a loop statement, so that up and down queries can be realized by changing a certain variable. The change of this variable is placed in the external interrupt program.

2 Hardware Circuit Design

Hardware circuit design Since the 51 single-chip microcomputer selected is a TTL device, and the NAND Flash memory to be detected is a CMOS device, the voltage levels of these two types of devices do not match, so it is necessary to add a level converter 74154245 to achieve bidirectional conversion between 5 V and 3 V voltage.

2.1 MCU connection

In order to facilitate reading, many wire connections in the circuit schematics of the system design are network labeled, and the naming of the labels is basically based on the pin name. The bit operation of the P1 port of the single-chip microcomputer controls the control end of the Flash, and the P0 port is used as the address and data transmission port of the single-chip microcomputer and the Flash. The flow of data is controlled by P1.6 and P1.7. When reading the data of the Flash, such as reading the ID, first operate the P1 port bit of the single-chip microcomputer, set the control word according to the timing, and then the PO port of the single-chip microcomputer outputs the command to read the ID, and then set the control word of the write address, and input the address 00H. In the read state, continuous RE pulses can output the ID code. The page read operation is similar. Figure 2 is a single-chip microcomputer circuit connection diagram.

2.2 Flash memory connection

K9K8G08UOM is a 1 GB high-capacity, high-reliability, non-volatile Flash memory using NAND technology, with high density and high performance. Its invalid block is defined as containing one or more invalid bytes, and its reliability cannot be guaranteed. The information in the invalid block is called invalid block information. Like all valid blocks, it has the same AC and DC parameters. An invalid block will not affect the operation of the valid block because it has corresponding independent instruction resources relying on the selection transistor. The system design must mask its invalid block through the address. In order to ensure that the first block (address is OOh) is a valid block, no error correction l K programming/erase cycle is required.

In addition to the invalid block information that has been loaded first, all storage units of the device are erased, and the invalid block status is defined in the first byte of the free area. There is no FFh in the column address of the 2048-byte first page of each block. In many cases, the invalid block information can also be erased. Once erased, it is impossible to restore its original information. Therefore, the system must recognize the invalid block based on the information of the original invalid block. The system is designed to determine whether the block is an invalid block by reading the first page of each block.

According to the function of each pin in the Flash device data sheet, the circuit connection of Flash is designed. Figure 3 only shows the pins used by the K9K8G08UOM part. The control end of the Flash in the circuit is connected to the Pl port of the microcontroller through a level converter, and the I/O port is connected to the P0 port of the microcontroller through a level converter.

2.3 74LVX4245 Level Converter

The 74LVX4245 provides an 8-bit bidirectional level converter that converts between 5V and 3V. The T/R pin of this device controls the direction of data flow. The transmitter makes data flow from terminal A to terminal B, while the receiver makes data flow from terminal B to terminal A. Terminal A is connected to the 5V bus, while terminal B is connected to the 3V bus, as shown in Figure 4. [page]

2.4 Digital Tube

The common anode digital tube dynamic display mode is adopted. In order to improve the driving ability, a triode drive is adopted, and the digital tube is lit bit by bit with the low level of the P2 port, and the character to be displayed is input into the P0 port. When this system is designed, the first and second bits show the number of bad blocks, and the last three bits show the invalid block address.
  

3 System Software Design

The μVision2 integrated development environment is used. μVision2 supports all Keil toolkits for 8051, including C editor, macro assembler, linker, locator and converter from object file to HEX format. System software design, that is, microcontroller code design, can usually use assembly language or C language. Figure 5 is the main process of invalid block judgment.

The core part of the software in this design is the page read function of the memory. The function defines an unsigned integer variable with a value of 2048. According to the timing of page read, the read instruction 00H is first written into the command register of the Flash by the function Writ-eCommand, and then the address of 4 cycles is written into the address register of the Flash by the WriteAddress function, and then the read command 30H is written into the Flash instruction register by the WriteCommand function. After the delay, the control word of the read status is set, and the cache data is read in 2048 read signal pulses. The complete source code of this function is as follows:

4 Conclusion

This design meets the system design requirements, can read the ID number of the Flash memory, accurately read the number of invalid blocks in the memory and the corresponding physical address, and query the invalid block address up and down through the function button. After replacing the memory with fLash, the distribution of invalid blocks of the device can be well detected. It can be a tool for selecting devices with better performance, and can also accurately obtain the invalid block address, laying a good foundation for future data storage.