The instruction fetching and execution sequence of 80C51 single-chip microcomputer instructions

Use the ALE signal as the latch control signal for the lower 8-bit address. When ALE is connected to an external latch, during the high level period, the p0 of 51 outputs the address, and during the low level period, the latch latches the address. When ALE is low (PSEN is low), the p0 port can transmit data (instructions), so that address/data multiplexing is possible.

The PSEN signal is used as the read select signal of the extended program memory. When reading the external ROM, PSEN is valid at a low level to implement the ROM read operation.

The EA signal is used as the selection control signal for the internal and external program memory. When it is at a low level, the read operation of the ROM is limited to the external program memory. When it is at a high level, the read operation of the ROM starts from the internal memory and can be extended to the external program memory.

The RD and WR signals are used as read enable and write enable signals for the extended data memory and I/O port.

The EA signal is a control signal indicating whether the current instruction is to read the internal or external memory. For example, when a microcontroller without internal memory is selected, or when the internal memory is not to be used, EA must be connected to a low level. In addition, the starting address of the external program memory should be arranged after the internal memory.

The RD and WR signals are relatively easy to understand, that is, they are valid when reading data (regardless of internal or external, RAM or ROM). The same is true for WR.

The instruction fetching and execution sequence of 80C51 single-chip microcomputer instructions

Now we will introduce the CPU timing according to the four types of instructions. Because the CPU works by fetching and executing instructions, the CPU must first fetch instructions before it can execute them.

1. Double-byte single-cycle instructions

Since the double-byte single-cycle instruction must fetch the machine code twice in one cycle, the operation of reading the opcode twice must be arranged in one machine cycle, which occurs at S1P2 and S4P2 respectively. The machine code 74 is read in S1P2 and sent to the instruction register IR, and the data 03 is read in S4P2 and sent to the accumulator A, that is, read 2 and take 2. During the execution of the instruction, the P0 port must transmit the address and data in time. Therefore, when the address of the opcode is output from the P0 port, the address latch signal ALE must be sent to the 74LS373 latch to latch the address in the 74LS373, freeing up the P0 port to read the machine code 74. The ALE signal must also be sent when fetching data 03. Therefore, the address latch signal is valid twice in one machine cycle, see the 80C51 timing diagram 2-13.

2. Single-byte single-cycle instruction

For single-byte single-cycle instructions, since the opcode is only one byte, the first read opcode is valid, while the second read opcode will be discarded, that is: read 1 and discard 1, and the program counter PC will not increase by 1.

3. Single-byte two-cycle instruction

For single-byte two-cycle instructions, since the opcode is only one byte and the execution time is as long as 2 machine cycles, the opcode is discarded except for the first read opcode, that is: read 1 and discard 3.

4. Access external memory instruction MOVX

When executing the instruction MOVX to access external memory, the instruction is first fetched from the program memory, and then the data is fetched from the external data memory, so the execution timing diagram of this instruction is different from the previous three types of instructions. Since MOVX is a single-byte two-cycle instruction, it reads 1 and loses 1 in the instruction fetch stage (i.e. S1P1 to S4P2 of the first machine cycle), and the operations completed in the instruction read data stage (i.e. S5 of the first machine cycle to S3 of the second machine cycle) are as follows:

(1) First, the address ADDR of the external data storage unit is output from the P0 and P2 ports by DPTR, which is the S5P1 to S6P2 stage in the timing diagram. And in the S4P2 to S5P2 stage, the ALE signal is sent to latch the address.

(2) In the second machine cycle S1P2 to S2P2, ALE and program selection signal PSEN are canceled (i.e. instruction fetch operation is canceled), so that port P0 is used exclusively for data transmission. At the same time, a read signal is sent to transfer the data in the external data storage unit to accumulator A through port P0. That is, the S6P2 to S4P1 stage of the timing diagram. [page]

(3) Since the latched address is the address of the external data storage unit, the instruction fetch operation is canceled in the second machine cycle S4, that is, the program selection signal PSEN is no longer sent.

Note: Since the ALE signal is sent one less time in the second machine cycle when executing the MOVX instruction, the frequency of ALE is unstable.