Based on LED display software design

　　The DMA controller inside S3C44BOX is used to transmit and control data, which simplifies the display program. The program flow is shown in the figure. The transmission of the dot matrix code is completed by the DMA controller. Before starting the DMA data transmission, you only need to assign the first address of the dot matrix code, the first address of the LED display screen and the value of the transmission data volume to the corresponding control word, and start the DMA operation. After completing the transmission of all the dot matrix codes of the same name row, the refreshed data is latched into the second-level column data latch and output to drive the display of the same name row. In this way, after 16 rows of the same name are displayed in a loop, a frame of dot matrix display is completed.

　　2. Dot Matrix Sorting

　　Due to the circuit structure of the LED display module and the use of 16-bit parallel bus and DMA data transmission technology, the order of dot matrix code during display needs to meet the following requirements:

　　① A series of horizontal cascade levels of two adjacent vertical cascades should be arranged in dot matrix order according to the principles in ① and ②.

　　Figure shows the program flow chart

　　② Due to the structure of the first-level column data latch decoding selection circuit of the display driver module and the DMA data transmission requirements, the same-name row dot matrix of the upper and lower parts of the same display driver module should be stored continuously in sequence according to the selection order of the column data latch.

　　③16-bit parallel bus transmits data once, that is, one DM write operation transmits two bytes of dot matrix code, and the low-order and high-order bytes are respectively sent to the same-name row and column data latches of two adjacent vertical cascade modules. Therefore, the same-name row and column dot matrix codes of the corresponding vertical cascade modules should be stored continuously.

　　④ In the 16-line scanning display mode, a large LED is divided into 16 rows with the same name, and each row with the same name is arranged in dot matrix according to the principles in ①, ②, ③, and ④.

　　⑤ Each vertical cascade level shall sort the dot matrix code according to the principles in ①, ② and ③.

　　Taking the data sorting of the first row of the same name of a 128×64 pixel dot matrix screen as an example (as shown in the figure), the storage order of the dot matrix codes of the first row of the same name should be: a, b...z, A, B...Z...

　　Figure 128×64 pixel dot matrix screen first row of the same name dot matrix code sequence diagram

　　The use of parallel bus DMA data transmission technology simplifies the software and hardware design of the LED display system, reduces the system cost, and can achieve good display quality. Under the system clock of 22.1184MHz, the display frame rate of the 512×256 pixel monochrome dot matrix screen reaches 250Hz, and an average of 120ns is used to transmit 1 byte, reaching the goal of using a single CPU system instead of a multi-machine system to control the LED display system. However, in order to make the previous generation of display driver boards still usable, the dot matrix code needs to be sorted, and can only be displayed in page mode, so a large capacity memory is required for multi-page dynamic scrolling display. For a 512×256 pixel monochrome dot matrix screen, tens of megabytes of capacity are required. The advanced controller S3C44BOX with a 32-bit ARMTTDM 1 core and cheap large-capacity SDRAM can solve this problem well.

　　If a display driver board designed for DMA control display is used, the dot matrix code does not need to be sorted, and a SRAM of several hundred kilobytes can meet the system requirements.

　　The so-called DMA (direct memory access) is a high-speed data transfer operation that allows data to be read and written directly between external devices and memory, without going through the CPU or requiring CPU preparation. The entire data transfer operation is carried out under the control of a "DMA controller". In addition to doing some processing at the beginning and end of data transfer, the CPU can do other work during the transmission process. In this way, most of the time, the CPU and input and output are in parallel operation. Therefore, the efficiency of the entire system is greatly improved. Because DMA allows peripherals to directly access memory, thereby forming an exclusive use of the bus, this will cause excessive interrupt delays in the embedded development of hard real-time systems with strong real-time performance, which is not allowed in some important occasions (such as government headquarters, finance, military, etc.) systems.