HPI Communication Design Based on TMS320VC5402 Single Chip Microcomputer

    This article introduces the interface circuit between the DSP at the end of the satellite CDMA receiver and the microcomputer serial port communication that I am developing. Since the CDMA receiver supports the reception of two independent CDMA channels and sends the demodulated data of the two channels to different computers through the serial port for subsequent processing, the receiver needs to have two RS232 interfaces. 

    There are usually three ways for the asynchronous serial port of a microcomputer to communicate with a DSP processor. The first method is to use an asynchronous communication chip to expand the serial port, such as using TI's TL16C550 to complete the serial/parallel and parallel/serial conversion of data. Since TL16C550 provides a wealth of control pins and response signals, it only needs to set some registers to control it flexibly, so programming is relatively simple, but the reading or writing of its data requires the use of the DSP's data bus. The second method is to use the DSP's I/O port XF and , or the DSP's McBSP port to simulate an asynchronous serial port with software. In this method, although there is no need for a serial/parallel conversion device between the DSP and the microcomputer serial port, the hardware structure is very simple, but the programming of the DSP is relatively complicated. Using the I/O port line to simulate the serial port requires two timer resources, and this method is only feasible when the DSP operation is not busy. The third method is to use a single-chip microcomputer to achieve serial/parallel and parallel/serial conversion of data. Compared with the first method, this method increases the programming of the MCU, but the MCU can be used as a controller to operate the HPI port of the DSP. The data transmission and reception of the DSP memory can be completely initiated by the MCU, and the DSP does not need to do any operation or use the data bus. This method is particularly useful when the DSP processing process is complex and the amount of calculation is large. 

    In this system, we use the high-performance, low-power DSP processor TMS320VC5402 to realize the system's MAC layer control and data encoding and decoding work, and the processor has a lot of work. In addition, the DSP data bus needs to exchange data with the FPGA chip (APEXEP20K600E) as the baseband processor. In order to avoid introducing additional control logic to achieve data bus multiplexing, the method of using a single-chip microcomputer to control the HPI port is used to realize the communication between the DSP and the dual serial port. Considering the existence of FPGA chips and cost savings, we did not use the expensive dual-serial port single-chip microcomputer (such as DS80C320) that requires advanced simulator development, but used two AT89C2051s and borrowed the redundant resources of the physical layer FPGA as the bus arbitrator to achieve the same function. 

1 TMS320VC5402 Introduction

　　TMS320VC5402 is a new product in TI's C54x series of fixed-point DSP chips. It concentrates the advantages of the earlier products in this series and provides many new functions, making it more convenient to develop and use. C5402 has a flexible instruction system and operating performance. It can select mnemonic instructions or arithmetic instructions as programming instructions, and supports separate or mixed programming of assembly language and C language. C5402 adopts an improved Harvanl processing structure and instruction pipeline operation. The calculation and processing speed is very high, and the system single instruction cycle can reach 10ns. 16k RAM is provided on the chip for program and data storage, and its maximum expandable addressing space is 1M bytes. The McBSP serial port and DAM data transmission method provided by C5402 greatly facilitate its application and development in the field of communications. C5402 has become the current mainstream product for language and static image processing due to its high performance and price.

2 TMS320VC5402 HPI port structure

    HPI (Host Interface) is an 8-bit parallel data port for data exchange between the host and TMS320VC5402. This interface is on the TMS320VC5402 chip, and has data registers (HPID), control registers (HPIC) and address registers (HPIA) inside. The HPI port can transmit 16-bit data using 8-bit data lines, and can control the high 8-bit and low 8-bit transmission by setting the relevant bits of the control register. HPI has two working modes: one is the host exclusive mode (HOM); the other is the host and TMS320VC5402 shared mode (SAM). Among them, SAM is a common mode, and both can address the HPI memory (DARAM). When the two conflict, the host has a higher priority, and a waiting cycle is inserted in the TMS320VC5402. The data rate transmitted through HPI is 1 byte per 5 CLKOUT clock cycles.

　　HPI communication is mainly achieved by assigning values ​​to the three registers HPIA, HPIC and HPID. Simply put, after the HOST selects different registers through the external pins HCNTL0 and HCNTL1, the current 8-bit data is sent to the register. Since HPIC is a 16-bit register and the HPI port always transmits 8-bit data width, when the HOST writes data to HPIC, two identical 8-bit data need to be sent. For TMS320VC5402, only the lower 8 bits are meaningful. After the address register HPIA is selected, data can be written directly to it, but the order of MSB and LSB should be paid attention to. In addition, HPIA has the feature of automatic growth, that is, HPIA will automatically increase by 1 before each data is written and after each data is read. In this way, if this function is used, you only need to set HPIA once to realize the writing and reading of continuous data blocks, but when implementing it, the data should be sent from the host to HPID first, and then the data in HPID should be written to the address of the on-chip RAM according to the address specified by HPIA.

    The HPI interface also provides interrupt logic to perform software handshake with the host. The host can interrupt the DSP chip by setting the second bit (DSPINT) of the control register HPIC to 1; the DSP chip can interrupt the host by setting the third bit (HINT) of HPIC to 1. At this time, the HPI pin is set to a low level, thereby sending an interrupt request to the host; the host can also set the HPIC bit HINT to 1 to return the pin to a high level, thereby clearing the interrupt signal. 

    The following is a description of the HPI port related pins: 

    HD0~HD7 are 8-bit bidirectional data lines connected to the P1 port of the microcontroller for exchanging data. 

    The combination of HCNTL1/0 is used to select the HPI register accessed by the host. 00 indicates that the host accesses HPIC; 10 indicates access to HPIA; 01 and 11 both indicate access to HPID, but 01 also indicates that the HPIA automatic growth function is enabled at the same time. 

    When 16-bit data is transmitted, HBIL is 0, indicating that the first byte is transmitted, and 1, indicating that the second byte is transmitted. The byte in which the high 8 bits are located is determined by the BOB bit in HPIC. 

    HPI provides two latching modes. One is to latch each control signal by the falling edge of (host address latch signal); the other is to complete it by the latter three together, and latch each control signal by the falling edge of any one of them. We use the second mode, and the latching of the control signal is completed by the low jump of . This latching signal also indicates the start of an HPI port operation process. 

    HRDY is the ready indication for HPI. 

    This is the pin through which the DSP sends an interrupt to the host. 

    HPIENA is the HPI enable control signal, and a high level enables HPI operation. 

3 MCU I/O port allocation, wiring and programming 

3.1 MCU I/O port allocation

    In this system, considering the area of ​​the board, the small AT89C2051 microcontroller was selected, and the P0 and P2 ports were omitted. A precision analog comparator was added. In addition to being used as I/O ports (external resistors are required to pull up), P1.0 and P1.1 are also used as the positive and negative inputs of the comparator, while P3.6 is specifically used as the comparator output. Therefore, AT89C2051 provides 15 bidirectional I/O port lines. In addition to P3.0 and P3.1 used as asynchronous serial ports and P1.0~P1.7 used for data bus communication with the HPI port, there are 5 I/O port lines available. Since it is also necessary to control the various control signals of the HPI port and the handshake signals with the DSP, the remaining 5 I/O port lines are obviously not enough, so a latch is also designed in the FPGA to use the P1 port as a control/data multiplexing port. The specific I/O port signal allocation is as follows: 

    P1.0~P1.7 are connected to the data lines HD0~HD7 of the HPI port. When used as control signal multiplexing, 

    P1.0 is connected to the latch signal of the latch in the FPGA; 

    P1.1 is latched by FPGA and controls HCNTL0; 

    P1.2 is latched by FPGA and controls HCNTL1; 

    P1.3 is latched by FPGA and controls HBIL; 

    P1.4 is latched by FPGA and controls

    P3.2 is connected to HPI ; 

    P3.3 connects to HPI's XF; 

    P3.4 is connected to HRDY of HPI; 

    P3.5 is the microcontroller request to send a signal, connected to P3.5 of FPGA; 

    P3.7 latches the control signals of HPI through FPGA control

Figure 1 shows the connection diagram between the HPI interface and two AT89C2051 chips. [page]

3.2 Key points of single chip microcomputer programming

    As mentioned above, P3.5 is the sending request signal of the microcontroller. When there is no data to send, it is high level. When it is low level, it means that the microcontroller wants to send data and applies to the bus arbitrator for the use of the bus. The bus arbitrator determines who can use the bus at present, and then interrupts the DSP processor through external interrupt 0. At the same time, it informs the DSP through the port which microcontroller can currently use the bus. Finally, the DSP centrally controls the bus use right of the microcontroller through the XF pin. After the microcontroller obtains the right to use the bus and sends the data, it writes 1 to the DSPINT bit of the HPI control register and notifies the DSP with an interrupt. When the microcontroller needs to receive data, the DSP first sets the XF pin to select which microcontroller to receive, and then sets the pin to low, and informs the microcontroller to receive through an interrupt. When the microcontroller receives from the HPI port, P3.5 should also be set low to keep the microcontroller selection signal of the bus arbitrator consistent with the XF pin. 

    When programming a microcontroller, the following points should be noted: (1) Since two microcontrollers share a bus, in order to ensure that they do not interfere with each other, the P1 port of the microcontroller that does not use the bus must be in a high-impedance state. According to the internal structure of the P1 port, when the microcontroller does not use the bus, this purpose can be achieved by writing 0xFF to the P1 port. (2) Since the P1 port is a control/data signal multiplexing port, when programming, for each HPI port operation, the control signal is first sent to the P1 port, and then P1.0 is set to generate a low-to-high transition, and the P1.1-P1.4 signals that control the HPI port are latched into the latch inside the FPGA. Only then can the P1 port be used as a data port, and after a low transition is generated on P3.7, a data transfer is initiated. (3) When programming, the microcontroller should be prevented from being required to perform both receiving and sending operations on the HPI port at the same time. This can be handled flexibly according to the actual situation. Due to space limitations, it will not be elaborated. 

4 Design of bus arbiter

    The function of the bus arbiter is mainly to select the microcontroller that can currently use the bus according to the bus request signal of the microcontroller P3.5. The design of the arbitrator must ensure that the microcontroller can compete fairly for the right to use the bus. In the case of two microcontrollers competing for the bus, a simple state machine can achieve the purpose. The state machine state has only two states, S0 and S1. When P3.5 is high, the bus is not requested and the state machine remains in the original state; when P3.5 is low, the state machine switches to the corresponding state according to the microcontroller currently requesting the bus. If the microcontrollers apply to use the bus at the same time, the current state remains unchanged. The state transition table is given below (S0 means selecting microcontroller 1, S1 means selecting microcontroller 2): 

    state,   MCU1_P3.5,   MCU2_P3.5     => state; 

     S0,        0,           x          =>  S0; 

     S0,        1,           0          =>  S1; 

     S0,        1,           1          =>  S0; 

     S1,        x,           0          =>  S1; 

     S1,        0,           1          =>  S0; 

     S1, 1, 1 => S1; 

    When the state machine changes state, the FPGA generates a low-level pulse with a pulse width of about 1μs. This signal is connected to the DSP external interrupt pin to interrupt the DSP and inform the DSP of the current state of the state machine through the pin, indicating the microcontroller that is requesting to use the bus. 

    In addition, as mentioned above, a latch is set inside the FPGA to latch the HPI port control signal sent from the P1 port by the high jump of P1.0. As for the two P3.7 signals of control, they only need to be ANDed inside the FPGA. 

4 Hardware connection between MCU and microcomputer serial port

    In the IBM PC/XT microcomputer system, its serial port complies with the RS-232C interface standard. In order to improve the anti-interference ability, the RS-232C standard adopts negative logic, the low level between -5V and -15V (usually expressed as -12V) is logic "1", and the high level between +5V and +15V (usually expressed as +12V) is logic "0". The above level is called EIA level, which is different from TTL level and CMOS level. In order to enable AT89C2051 to communicate serially with the microcomputer, MAX232 can be used to complete the conversion between RS-232C level and TTL level.

    After the microcontroller program completes the initialization process such as the working mode and baud rate setting of the serial port, it can start communicating with the serial port. There are two communication modes: query mode and interrupt mode. Since the query mode requires the CPU to continuously query the flag bit, the program efficiency is not high. Therefore, the interrupt mode is usually used when the microcontroller operation is relatively busy. The specific programming application will not be introduced here.

    This paper introduces the design method of using FPGA chip as bus arbiter to realize the communication between the dual serial ports of microcomputer and DSP HPI port through AT89C2051. Compared with the circuit using special chip, this circuit is not complicated and more practical. Since the data exchange between DSP memory and DSP memory is completely initiated by single chip microcomputer, DSP can be freed from data transmission to complete more complex control and calculation. Practice has proved that this circuit can meet our design requirements well. Under the condition of asynchronous data transmission rate of 9600bps, it can reliably realize the communication between the dual serial ports of microcomputer and DSP.

References:

[1]. AT89C2051 datasheet http://www.dzsc.com/datasheet/AT89C2051_.html.
[2]. RS232 datasheet http://www.dzsc.com/datasheet/RS232_585128.html.
[3]. TL16C550 datasheet http://www.dzsc.com/datasheet/TL16C550_.
[4]. TTL datasheet http://www.dzsc.com/datasheet/TTL_1174409.html.
[5]. MAX232 datasheet http://www.dzsc.com/datasheet/MAX232_1074207.html.