Design of interface between dual-port RAM and PCI9052 based on FPGA

O Introduction
The access time of IDT70V28L (dual-port RAM) is greater than 20ns. PCI9052 works at 25MHz, and its access time is greater than that of dual-port RAM. PCI9052 is the initiator of the transaction, which is equivalent to a slow device accessing a fast device. Through programmable devices, the read and write control signals of PCI9052 can be directly transmitted to IDT70V28L to complete the timing matching.
In order to convert the local logic of PCI9052 into the read and write control signals and address signals of dual-port RAM, this design uses programmable devices to implement the interface logic circuit between them. In the design of programmable devices, the design method of state machine is one of the most widely used design methods. Finite state machine is a simple, clear structure, and flexible design method. It is easy to establish, understand and maintain. It is especially used in systems with a large number of state transitions and complex timing control, which shows its advantages. In view of its advantages, this design uses the state machine described by Verilog HDL to implement the timing logic of the interface, and verifies the correctness of the design through simulation tools.

1 PCI9052 and Dual DRAM
1.1 Introduction to PCI9052
PCI9052 is a low-cost bus target interface chip developed by PLX after PCI9050. It has low power consumption and complies with PCI2.1 specification. Its local bus (LOCAL BUS) can be programmed to be an 8/16/32-bit (non-) multiplexed bus, and the data transmission rate can reach 132Mb/s. Its main functions and features are as follows:
(1) Asynchronous operation. The clocks of the PCI9052 Local Bus and the PCI bus run independently of each other. The asynchronous operation of the two buses facilitates the compatibility of high-speed and low-speed devices. The operating clock frequency range of the Local Bus is 0-40MHz, TTL level; the operating clock frequency range of PCI is 0-33MHz.
(2) Programmable local bus configuration. PCI9052 supports 8-bit, 16-bit or 32-bit Local Bus, which can be multiplexed or non-multiplexed. PCI9052 has 4 byte enable (LBE[3:0]#) signals, 26 address lines (LA[27:2]), and 32-bit, 16-bit, and 8-bit data lines (LAD[3l:0]).
(3) Direct slave (target) data transfer mode. PCI9052 supports burst transfers and I/O accesses from the PCI bus to the Local Bus's memory-mapped space. Read and write FIFOs allow high-performance bursts between the PCI and local buses. The PCI bus is allowed to burst, so the Local Bus can be set to burst or last a single cycle.
(4) 4 local chip selects. PCI9052 provides 4 chip selects, and the base address and range of each chip select are programmed independently by SEEPROM or the host.
(5) 5 local address spaces. The base address and range of each local address space are programmed uniquely by SEEPROM or the host.
1.2 Dual-port RAM
IDT70V28 is a high-speed 64k×16 dual-port static RAM. It can be designed as a 1024kb dual-port RAM or a 32-bit word master-slave dual-port RAM. The dual-port RAM provides two independent ports with control, address and I/O pins. Its main features are as follows: a. Can access the same memory space of dual ports at the same time; b. High-speed storage access, the access speed can reach 20ns; c. Low power operation; d. By cascading multiple devices, the data line width can be easily expanded to 32 bits or higher; e. With 'busy' and 'interrupt' flags. Avoid access conflicts: f. Can access ports independently. [page]

2 Interface design between PCI and dual-port RAM
In order to solve the problem of mismatch in read and write timing between PCI9052 and dual-port RAM, the programmable logic device CYCLONE-II is used to implement the interface circuit between them, and its signal connection relationship is shown in Figure 1.

PCI9052 needs to issue read and write instructions to the dual-port RAM after the FPGA is configured. This can be determined by querying CONF_DONE (connected to USER1) and INIT_DONE (connected to USER3) to determine whether the FPGA is configured. If the INIT_DONE signal is sampled and it is high, it indicates that the FPGA configuration is complete; if the CONF_DONE signal is sampled and it is high, the PCI9052 needs to wait for tCD2UM (min=18 μs, max=40 μs) before it can read and write the dual-port RAM. The dual-port RAM uses IDT70V28L, and its access time is greater than 20ns. PCI9052 adopts non-multiplexed, single-cycle read/write mode and works at a 25MHz clock. PCI accesses the memory with a 32-bit width. Each read and write operation corresponds to two 16-bit operations on the Local Bus. In order to prevent conflicts between adjacent secondary transactions, each state machine starts a read and write access by detecting that the ADS signal is valid, and inserts an NXDA wait cycle. The specific read and write operation implementation process is as follows.
2.1 PCI9052 write process
The write process is described by a state machine, which has 6 states: write idle, write start, write wait data, write process, write process wait and write end. The specific state transition diagram is shown in Figure 2.

After the system is reset, BTERM and MS are pulled high, LHOLD and MODE are pulled low, the write control signal is invalid, and the state machine is in the write idle state.
When the state machine is in the write idle state, each time the rising edge samples that ADS is valid and LWR is high, and the dual-port RAM space is accessed (CS0 or CS1 is valid), the state machine enters the write start state. In the write start state, the state machine waits for certain operations without performing them. Next is the write wait data state, at which SEML, CEOL, and CElL are translated according to the values ​​of the chip select signals CS0 and CS1, and valid addresses and control signals RWL, UBL, and LBL are output to the dual-port RAM. Next is the write process state. In order to obtain valid data, this process does not operate on input and output. Then comes the write process wait state, at which the LRDY signal is set valid and valid data is output to the dual-port RAM. Finally, it is the write end state, in which the chip select signals CEOI., CElL, and SEMI. are set invalid. In the next cycle of this process, the remaining write control signals are set invalid, and the state machine returns to the write idle state.
2.2 PCI9052 Reading Process
The reading process is also described by a state machine, which has 6 states, namely, read idle, read start, read waiting data, read process, read process waiting and read end. Its state transition is shown in Figure 3.

When the system is reset, BTERM and MS are pulled high, LHOLD and MODE are pulled low, the read control signal is invalid, and the state machine is in the write idle state.

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When the state machine is in the read idle state, the state machine switches to the read start state when ADS is valid and LWR is low level at each rising edge sampling, and the dual-port RAM space is accessed (CS0 or CS1 is valid). Next is the read wait data state, at this time, SEML, CE0L, CElL are translated according to the values ​​of the chip select signals CS0 and CS1, and valid address and control signals RWL, UBL, LBL, OEL are output to the dual-port RAM. Next is the read process state. In order to obtain valid data, this process does not operate on input and output. Then comes the read process wait state. At this time, the LRDY signal is set valid and valid data is output to PCI9052. Finally, it is the write end state. In the next cycle of this process, the read control signal is set invalid and the state machine returns to the read idle state.

3 FPGA simulation implementation
Under the Modelsim development platform, the simulation process of PCI9052 reading and writing dual-port RAM is implemented, and the simulation waveform is shown in Figure 4. From the simulation waveform, it can be seen that the code can convert the read and write control signals of PCI90-52 into the read and write control signals of dual-port RAM, completing the timing matching.

4 Conclusion
This design uses a programmable logic chip to implement the interface circuit of PCI accessing dual-port RAM. The interface circuit is modifiable and applicable. With the development of microelectronics technology, the capacity of programmable devices has reached tens of millions of gates. More and more tasks that had to be completed by dedicated chips or devices in the past can now be implemented by FPGA through software design. The softwareization of hardware has become an unstoppable trend in the electronics industry.