Interrupts are closely related to stack settings and ARM architecture. ARM is a system kernel that supports multi-tasking operations, and its internal structure is fully adapted to multi-tasking applications. The ARM kernel supports 7 types of interrupts. Different interrupts are in different processing modes (as shown in Table 1), have different priorities, and each interrupt has a fixed interrupt entry address. When an interrupt occurs, the corresponding R14 (LR) stores the interrupt return address, and the SPSR stores the value of the status register CPSR.
Since the ARM core supports pipeline operation, the address stored in the LR register may be the address of the instruction following the interrupt. Therefore, after different interrupts are processed, the LR register value must be processed and then written to the R15 (PC) register.
Table 1 ARM's 7 interrupts
The exceptions supported by the ARM architecture and their specific meanings are shown in Table 2.
Table 2 Exceptions supported by ARM and their specific meanings
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MODE_Switch1Processing multi-interrupt request needs to set the priority of these interrupt requests
IIC Comunication
Input subsystem explanation
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