Instruction timing of MCS-51 microcontroller

Timing is described using timing units. MCS-51 has four timing units: beat, state, machine cycle, and instruction cycle. We will explain each of them below.

• Beat and state:
  We define the period of the oscillation pulse as the beat (represented by P for the convenience of description). After the oscillation pulse is divided by two, we get the clock signal of the entire microcontroller working system. The period of the clock signal is defined as the state (represented by S). Such a state has two beats. The beat corresponding to the first half of the cycle is defined as 1 (P1), and the beat corresponding to the second half of the cycle is defined as 2 (P2).
• Machine cycle:
  MCS-51 has a fixed machine cycle, which stipulates that a machine cycle has 6 states, represented by S1-S6, and one state contains two beats, so a machine cycle has 12 beats. We can remember S1P1, S1P2...S6P1, S6P2. A machine cycle contains a total of 12 oscillation pulses, that is, the machine cycle is 12-divided by the oscillation pulse. Obviously, if a clock frequency of 6MHz is used, a machine cycle is 2us, and if a clock frequency of 12MHz is used, a machine cycle is 1us.
• Instruction cycle:
  The time required to execute an instruction is called the instruction cycle. MCS-51 instructions are single-byte, double-byte, and triple-byte, so their instruction cycles are not the same, that is, the machine cycles they require are different, and may include one to four machine cycles (we will explain these contents in the following chapters).

MCS-51 instruction timing:
In the MCS-51 instruction system, instructions can be divided into single-byte instructions, double-byte instructions and three-byte instructions according to their length. The time required to execute these instructions is different, that is, the machine cycles they require are different, and there are the following forms:

• Single byte instruction single machine cycle
• Single byte instruction double machine cycle
• Two-byte instruction single machine cycle
• Two-byte instruction, two machine cycles
• Three-byte instruction double machine cycle
• Single-byte instructions take four machine cycles (such as single-byte multiplication and division instructions)

The following figure is the instruction timing diagram of the MCS-51 series microcontroller:

The figure above shows the timing of single-cycle and double-cycle instruction fetch and execution. The ALE pulse in the figure is the selection signal for latching the address. Obviously, each time this signal appears, the microcontroller performs a read instruction operation. It can be seen from the timing diagram that this signal is obtained after the clock frequency is divided by 6. In one machine cycle, the ALE signal is valid twice, the first time during S1P2 and S2P1, and the second time during S4P2 and S5P1.
Next, we will explain several typical instruction timings.

• Single-byte single-cycle instruction:
  A single-byte single-cycle instruction only performs one read instruction operation. When the second ALE signal is valid, PC does not increase by 1, so the original instruction is still read, which is an invalid read operation.
• Double-byte single-cycle instructions:
  For this type of instruction, both ALE signals are valid, but when the first ALE signal is valid, the opcode is read, and when the second ALE signal is valid, the operand is read.
• Single-byte two-cycle instruction:
  Two machine cycles require four read instruction operations, but only one read operation is valid, and the next three read operations are invalid operations.
  There is a special case for single-byte two-cycle instructions, such as MOVX. When executing such instructions, the instruction is first read from the ROM, and then the external data memory is read or written. The opcode of the first read instruction in the first machine cycle is valid, while the second read instruction operation is invalid. In the second instruction cycle, the external data memory is accessed. At this time, the ALE signal has no effect on its operation, that is, there will be no more read instruction operation.

In the timing diagram on the previous page, we only described the instruction reading status, but did not draw the instruction execution timing, because each instruction contains specific operands, and the types of operands are too diverse to list here. Interested readers can refer to relevant books. [page]

External program memory (ROM) read timing

Figure 8051 external program memory read timing diagram. It can be seen from the figure that P0 port provides the low 8-bit address and P2 port provides the high 8-bit address. Before the end of S2, the low 8-bit address on P0 port is valid. After that, the low 8-bit address signal appears on P0 port, but the instruction data signal. Of course, there is a buffer transition time between the address signal and the instruction data signal. This requires that the low 8-bit address signal must be latched during S2. At this time, the ALE selection pulse is used to control the latch to latch the low 8-bit address. The P2 port only outputs the address signal, but there is no instruction data signal. The address signal is valid throughout the machine cycle, so there is no need to latch this address signal. To read instructions
from the external program memory, two signals must be controlled. In addition to the above-mentioned ALE signal, there is also a PSEN (external ROM read selection pulse). It can be clearly seen from the above figure that PSEN is valid from S3P1 until the address signal is sent out and the data of the external program memory is read into the CPU. Then the second read instruction operation is executed from S4P2.

External data memory (RAM) read timing

The above figure shows the 8051 external data memory read and write timing diagram. The instructions to be executed are read from the ROM, and the CPU's access to the external data storage is to read or write data to the RAM, which belongs to the instruction execution cycle. It is worth mentioning that read or write are two different machine cycles, but their timing is similar. We only analyze the RAM read timing.
The previous machine cycle is the instruction fetch stage, which reads the instruction data from the ROM, and then the next cycle begins to read the contents of the external data memory RAM.
After S4 ends, the address to be read from the RAM is first placed on the bus, including the low 8-bit address A0-A7 on the P0 port and the high 8-bit address A8-A15 on the P2 port. When the RD strobe pulse is valid, the RAM data is read into the CPU through the P0 data bus. The ALE signal of the second machine cycle still appears, and an external ROM read operation is performed, but this time the read operation is an invalid operation.
When writing to the external RAM, the CPU outputs WR (write strobe signal) to write the data to the external memory through the P0 data bus.