Design and implementation of radar intermediate frequency signal simulator based on DSP, DDS and ARM

Radar signal simulator is the product of the combination of simulation technology and radar technology. It generates radar echo signals through simulation methods so as to debug the radar system backstage under conditions that are not available in the front end of the actual radar system. With the advancement of digital technology and the use of high-speed and ultra-large-scale integrated circuits, radar signal simulation systems are developing in a flexible and universal direction. The author designed a capable parent radar intermediate frequency signal simulator based on PC+ARM+DSP+DDS architecture, introduced the hardware design of the system, and introduced the application of this system by taking the simulation of phase parameter pulse radar moving target signal as an example.

1 System structure design

The design of modern radar signal simulation focuses on the use of digital methods. With the development of real-time digital signal processing technology, the PC+DSP+D/A architecture has become the main way to implement radar simulators. Direct digital frequency synthesis technology (DDS) has become a leader in modern frequency synthesis technology with its excellent performance in frequency agility, phase continuity, relative bandwidth, high resolution and integration. It also provides a new option for the implementation of radar intermediate frequency signal simulation.

This design adopts the PC+ARM+DSP+DDS architecture. The PCM machine models and calculates the target and environment to generate a radar intermediate frequency signal simulation database. The DSP performs data scheduling, calculation and processing according to the simulated radar real-time status and the real-time characteristics of the target and environment, and finally forms the amplitude modulation, phase modulation, frequency modulation and other control words required to control the DDS, and generates radar intermediate frequency simulation signals through the DDS.

Due to the consideration of the universality of the simulator, the communication between the PC and the DSP is expected to not only change the parameters of the radar simulation signal in real time, but also adapt to the specific requirements of different radar systems and different signal processors, and facilitate the loading of new programs. Although program loading can be achieved through PCI (or CPCI) and the transmission rate is fast, it cannot work offline, and it is troublesome to plug and unplug, and cannot be used for notebook debugging. This design uses ARM as the main control module to control the USB interface device and the host port of the DSP to complete the loading of the program and the real-time setting of parameters.

2. Hardware Circuit Design and Implementation

This system mainly includes a main control module with ARM as the core, a real-time data processing module with DSP as the core, a signal generation module with DDS as the core, and a communication module and power supply system including USB, RS-232 and latch. The system block diagram is shown in Figure 1. [page]

2.1 Main control module

The system main control module is responsible for controlling and coordinating various tasks. ARM uses the S3C44B0X microprocessor produced by Samsung. Through the integrated phase-locked loop frequency multiplication system, the main frequency can reach 66MHz, the maximum external storage space is 256MB, the on-chip resources are rich, the peripheral control capability is strong, and the cost performance is high. It controls the USB module to receive the data and code of the radar simulation signal generated by the PC, controls the host port to load the DSP, and controls the UART to realize the real-time display of the working status on the PC.

2.2 Real-time data processing module

The real-time data processing module uses the radar signal simulation data generated by the PC to calculate the control word of the DDS according to the set radar working state and the real-time dynamics of the target and environment, and controls the three DDS to output the radar simulation signal. At the same time, it exchanges information with the signal processor through the serial port and provides the attenuation control signal to the processing board through the latch.

The DSP uses the TMS320C6416 from TI's C6000 series, with a system clock of 600MHz and a data processing rate of 4800MIPS. It provides a 32/16-bit host port and two independent external memory interfaces, of which EMIFA supports a 64-bit bus width.

2.3 Signal generation module

The DDS signal generation module uses three AD9852ASQ produced by ADI, which generate three intermediate frequency signals at the same time. According to the different radar systems and signal processor requirements, they can correspond to different signals, such as the radar's target echo, clutter and transmission signal, or the direct wave, target echo and multipath signal of the external radiation source radar, as well as the sum branch ∑, the pitch left branch Δα and the azimuth difference branch Δβ of the tracking radar echo signal.

The maximum operating frequency of AD9852 is 300MHz, and it can work in five modes: single frequency, FSK, Ramped FSK, Chirp, and BPSK. It has a rich register set, and can easily generate a variety of signals by setting the corresponding control words.

2.3.1 Bus and Timing Control Design

The frequency, phase and amplitude control word setting and control signal generation of AD9852 are completed by TMS320C6416. AD9852 can be regarded as an asynchronous storage device connected to the EMIFA of TMS320C6416. EMIFA adopts 32-bit bus.

AD9852 uses parallel input, bus width is 8 bits, and data transmission rate can reach 100MHz. In order to improve the speed of controlling DDS, this system adopts address bus multiplexing, data bus, and "splitting" technology. That is, the 6-bit address lines of three AD9852s occupy TMS320C6416 address bus A2~A7 at the same time, and their data lines occupy TMS320C6416 data bus D0~D7, D8~D15 and D16~D23 respectively. In this way, DSP can write to the I/O buffer registers of three DDS at the same time, improve bus utilization, and ensure the phase coherence of the output signals of three AD9852s. The schematic diagram of the interface between TMS320C6416 and AD9852 is shown in Figure 2. [page]

The control timing signals of the three AD9852 chips are generated by EPLD. This design uses the programmable logic device EPM7128AETC100 produced by ALTERRA to encode the high-order address signal, data signal and control signal of TMS320C6416, and generate control signals such as global reset, read/write enable, frequency or phase switching of the three AD9852 chips.

The data written into AD9852 is first stored in the I/O buffer, and when the I/O update signal arrives, it is written into the corresponding register to change the working state of AD9852. In this design, the I/O update signal can be generated by DSP after writing the control word, or it can be generated by EPLD by dividing the system clock. The selection of the two methods and the control of the frequency division multiple are also realized by EPLD's signal encoding of TMS320C6416.

2.3.2 Clock Design

The spectrum characteristics of the signal output by DDS depend to a large extent on the spectrum characteristics of the reference clock. Some main characteristics of the reference clock, such as phase noise, clock jitter, and frequency stability, are directly reflected in the output signal of DDS. Whether the clock circuit of DDS can be designed to achieve high stability, low noise, and precise synchronization directly affects the performance of this system. The reference clock of AD9852 can use single-ended input or differential input. Since differential signals can effectively suppress common-mode noise and electromagnetic energy leakage, according to the peak-to-peak requirements of AD9852 (>400mV), this design uses differential LVPECL logic.

This module uses a 40MHz crystal oscillator and outputs three synchronous clocks through the buffer CY2305, as shown in Figure 3. One of them is connected to SH853501, which converts one LVCMOS clock into three differential LVPECL clocks, and then transmits them to three AD9852s respectively, and forms the system clock of DDS through the on-chip phase-locked loop; one is given to the timing control module EPLD, which divides the clock signal to generate the I/O update clock of the three AD9852s; the other is used as a synchronous clock to supply the signal processor.

2.4 Communication Module

The USB communication protocol is used between the radar simulator and the CP machine, which is realized by S3C44B0X controlling the USB interface device ISP1581. The DSP can send target angle information to the signal processor by controlling the EPLD, or it can use the multi-channel buffer serial port to transmit target information to the processor. This system provides an attenuation control interface, where the DSP generates the corresponding attenuation control word and transmits it to the latch SN75LVC574 to control the digital controlled attenuator on the processor.

3 Simulation of moving target signal of coherent pulse radar

The three DDSs in this system and the EPLD that controls the refresh and working timing use the same clock source and provide a synchronous clock output to the signal processor. Therefore, this system can be used to design the simulation of intermediate frequency coherent radar signals. [page]



In this design, the signal processor uses the synchronous clock output by the signal simulator to divide it to generate a trigger pulse, which is sent to the external interrupt source 4 of the simulator DSP. The period of the trigger pulse corresponds to the PRT (pulse repetition period) of the radar signal. The period of the EPLD divided clock corresponds to the pulse width of the radar pulse signal. This signal provides the I/O update clock of AD9852 and is connected to the external interrupt source 5 of the DSP. Two DDSs are used. DDS1 simulates the echo of a moving target, and DDS2 simulates a clutter signal.

On the PC, according to the target and environmental characteristics to be simulated, the corresponding model is established to calculate and generate the amplitude control word storage of the target echo and clutter. The DSP main program first reads this data into SDRAM. Within the designed target angle range, each time a trigger signal is received, the DSP interrupt generates a target echo signal after a delay determined by the target distance. The frequency and phase of the signal contain the Doppler frequency information of the target movement, and the amplitude is read from SDRAM; the clutter is generated by the continuous output of DDS2, and the DSP enters an interrupt every other pulse duration to read SDRAM to change the amplitude of the clutter. The DSP main program and interrupt handler flow are shown in Figure 4.

The radar signal used in the above simulation process is a simple rectangular pulse, and the pulse width is equal to the period of the DDS update signal. If a large pulse width is used, the phase of the signal is changed according to the Barker code or M sequence when each DDS update clock arrives within the pulse width, and a phase-coded pulse compression signal can be simulated. When the AD9852 works in CHIRP mode, a linear frequency-modulated pulse compression signal can be simulated by setting the frequency step length and slope timing (i.e., the time the changing frequency stays at each frequency point) control word. In the same mode, if the frequency step length or slope timing control word is changed when each DDS update clock arrives within the pulse width, a nonlinear frequency-modulated pulse compression signal can be simulated, and its principle is shown in Figure 5.

This design has the following main features:

(1) Using the various working modes of AD9852, a variety of radar signals can be easily generated, and the frequency agility is fast, the phase is continuous during agility, and the frequency resolution is as high as 10-6Hz.

(2) Three DDSs are controlled simultaneously by TMS320C6416, with fast reading and writing speed, ensuring real-time performance and output signal phase parameters.

(3) By controlling the USB module and DSP host port through ARM, signal parameters can be modified and new programs and data can be loaded in real time.

(4) It adopts three-channel DDS and provides synchronous clock output, which ensures that it can meet the requirements of radars of different systems and is more universal.

Experimental and application results show that the system can simulate radar intermediate frequency signals of various systems, and it is convenient to switch between different signals and flexible to use. The system provides a universal hardware platform for radar intermediate frequency signal simulation. On this basis, by enriching and improving the software database, a universal radar intermediate frequency signal simulation system can be built.

References:

[1]. PCI datasheet http://www.dzsc.com/datasheet/PCI_1201469.html.
[2]. RS-232 datasheet http://www.dzsc.com/datasheet/RS-232_584855.html.
[3 ]. TMS320C6416 datasheet http://www.dzsc.com/datasheet/TMS320C6416_1078043.html.
[4]. AD9852ASQ datasheet http://www.dzsc.com/datasheet/AD9852ASQ_251858.html.
[5]. //www.dzsc.com/datasheet/AD9852_251856.html.
[6]. D15 datasheet http://www.dzsc.com/datasheet/D15_1092218.html.
[7]. CY2305 datasheet http://www.dzsc.com/datasheet/CY2305_815806.html.
[8]. ISP1581 datasheet http://www.dzsc.com/datasheet/ISP1581_410269.html.